24-Bit Digital Signal Processor

DSP56321T Features High-Performance DSP56300 Core ? 220/240 million multiply-accumulates per second (MMACS) (440/480 MMACS using the EFCOP in filtering applications) with a 220/240 MHz clock at 1.6 V core and 3.3 V I/O and a junction temperature range of 0–85°C ? Object code compatible with t

文件：2.1632 Mbytes 頁數(shù)：88 Pages

恩XP

24-Bit Digital Signal Processor

DSP56321T Features High-Performance DSP56300 Core ? 220/240 million multiply-accumulates per second (MMACS) (440/480 MMACS using the EFCOP in filtering applications) with a 220/240 MHz clock at 1.6 V core and 3.3 V I/O and a junction temperature range of 0–85°C ? Object code compatible with t

文件：2.1632 Mbytes 頁數(shù)：88 Pages

恩XP

24-Bit Digital Signal Processor

DSP56321T Features High-Performance DSP56300 Core ? 220/240 million multiply-accumulates per second (MMACS) (440/480 MMACS using the EFCOP in filtering applications) with a 220/240 MHz clock at 1.6 V core and 3.3 V I/O and a junction temperature range of 0–85°C ? Object code compatible with t

文件：2.1632 Mbytes 頁數(shù)：88 Pages

恩XP

24-Bit Digital Signal Processor

Overview This product has been discontinued. See DSP56321.\nThe 恩XP? DSP56321T, a member of the DSP56300 family of programmable Digital Signal Processors (DSPs), supports network applications with general filtering operations. The on-chip Enhanced Filter Coprocessor (EFCOP) executes filter algorithm \n?\n?\n?\n?\n?\n?\n?\n? \n?\nProgram RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable: \n\n \n\n \n \n\n Program \nRAM Size;

恩XP