24-Bit Digital Signal Processor

24-Bit Digital Signal Processor The DSP56309 is a member of the DSP56300 core family of programmable CMOS DSPs. The DSP56300 core includes a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56309 offers 100 MMACS at 3.0–3.6 V using an inter

文件：1.90848 Mbytes 頁數(shù)：108 Pages

FREESCALEFreescale Semiconductor, Inc

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24-Bit Digital Signal Processor

24-Bit Digital Signal Processor The DSP56309 is a member of the DSP56300 core family of programmable CMOS digital signal processors (DSPs). The DSP56300 core includes a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56309 offers 100 MIPS at 3.0

文件：4.3652 Mbytes 頁數(shù)：424 Pages

MOTOROLA

摩托羅拉

24-Bit Digital Signal Processor

Features 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation an

文件：2.35451 Mbytes 頁數(shù)：108 Pages

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24-bit General Embedded DSP

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24-Bit Digital Signal Processor

24-Bit Digital Signal Processor The DSP56309 is a member of the DSP56300 core family of programmable CMOS digital signal processors (DSPs). The DSP56300 core includes a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56309 offers 100 MIPS at 3.0

文件：4.3652 Mbytes 頁數(shù)：424 Pages

MOTOROLA

摩托羅拉

24-Bit Digital Signal Processor

24-Bit Digital Signal Processor The DSP56309 is a member of the DSP56300 core family of programmable CMOS digital signal processors (DSPs). The DSP56300 core includes a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56309 offers 100 MIPS at 3.0

文件：4.3652 Mbytes 頁數(shù)：424 Pages

MOTOROLA

摩托羅拉

24-Bit Digital Signal Processor

Features 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation an

文件：2.35451 Mbytes 頁數(shù)：108 Pages

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