5-43 MHz FPD-Link LVDS (3 Data 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

文件：867.7 Kbytes 頁數(shù)：26 Pages

TI

德州儀器

5-43 MHz FPD-Link LVDS (3 Data 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

文件：1.01342 Mbytes 頁數(shù)：18 Pages

NSC

國半

5-43 MHz FPD-Link LVDS (3 Data 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

文件：1.01592 Mbytes 頁數(shù)：18 Pages

NSC

國半

5-43 MHz FPD-Link LVDS (3 Data 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

文件：867.7 Kbytes 頁數(shù)：26 Pages

TI

德州儀器

5-43 MHz FPD-Link LVDS (3 Data 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

文件：867.7 Kbytes 頁數(shù)：26 Pages

TI

德州儀器

5-43 MHz FPD-Link LVDS (3 Data 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

文件：1.01592 Mbytes 頁數(shù)：18 Pages

NSC

國半

5-43 MHz FPD-Link LVDS (3 Data 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

文件：867.7 Kbytes 頁數(shù)：26 Pages

TI

德州儀器

5-43 MHz FPD-Link LVDS (3 Data 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

文件：867.7 Kbytes 頁數(shù)：26 Pages

TI

德州儀器

5-43MHz FPD 鏈接 LVDS（3 數(shù)據(jù) + 1 時鐘）至 FPD-Link II LVDS（嵌入式時鐘直流平衡)轉(zhuǎn)換器

The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-sampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream simplifies transferring the 24-bit bus over a single differ ? 5 MHz–43 MHz Embedded Clock & DC-Balanced Data Transmission (21 Total LVDS Data Bits Plus 3 Low Speed LVCMOS Data Bits)\n? User Adjustable Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive up to 10 Meters Shielded Twisted-Pair Cable\n? Supports AC-Coupling;

TI

德州儀器

Package：36-WFQFN 裸露焊盤；包裝：卷帶（TR） 功能：串行器 類別：集成電路（IC） 串行器，解串器 描述：IC LVDS/FPD 5-43MHZ LINK 36WQFN

TI

德州儀器