首頁 >DS90CF384MTDX>規(guī)格書列表
| 型號(hào) | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
絲?。?a target="_blank" title="Marking" href="/ds90cf384mtd/marking.html">DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit 文件：811.57 Kbytes 頁數(shù)：30 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/ds90cf384mtd/marking.html">DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit 文件：811.57 Kbytes 頁數(shù)：30 Pages | TI 德州儀器 | TI | ||
絲印：DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit 文件：811.57 Kbytes 頁數(shù)：30 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/ds90cf384mtd/marking.html">DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz General Description The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bit 文件：811.57 Kbytes 頁數(shù)：30 Pages | TI 德州儀器 | TI | ||
3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 文件：410.45 Kbytes 頁數(shù)：22 Pages | TI 德州儀器 | TI | ||
3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz 文件：410.45 Kbytes 頁數(shù)：22 Pages | TI 德州儀器 | TI | ||
Package：56-TFSOP（0.240"，6.10mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 專用 描述：IC INTERFACE SPECIALIZED 56TSSOP | TI 德州儀器 | TI |
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
NS/國半 |
23+ |
TSOP56 |
50000 |
全新原裝正品現(xiàn)貨,支持訂貨 |
詢價(jià) | ||
NS/國半 |
2023+ |
TSOP |
11000 |
AI智能識(shí)別、工業(yè)、汽車、醫(yī)療方案LPC批量及配套一站 |
詢價(jià) | ||
NS/國半 |
98+ |
TSOP |
171 |
詢價(jià) | |||
TI/德州儀器 |
12+ |
TSSOP-56 |
4 |
全新原裝進(jìn)口自家現(xiàn)貨假一賠十 |
詢價(jià) | ||
NSC |
25+ |
5 |
公司優(yōu)勢(shì)庫存 熱賣中!! |
詢價(jià) | |||
TI(德州儀器) |
24+ |
NFBGA-64(8x8) |
690000 |
代理渠道/支持實(shí)單/只做原裝 |
詢價(jià) | ||
Rochester |
25+ |
電聯(lián)咨詢 |
7800 |
公司現(xiàn)貨,提供拆樣技術(shù)支持 |
詢價(jià) | ||
TI |
25+ |
NFBGA-64(8x8) |
18746 |
樣件支持,可原廠排單訂貨! |
詢價(jià) | ||
TI |
25+ |
NFBGA-64(8x8) |
18798 |
正規(guī)渠道,免費(fèi)送樣。支持賬期,BOM一站式配齊 |
詢價(jià) | ||
National Semiconductor |
24+25+ |
16500 |
全新原廠原裝現(xiàn)貨!受權(quán)代理!可送樣可提供技術(shù)支持! |
詢價(jià) |
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