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                >DS90CF384MTD>規(guī)格書列表
                
    
            
    
                
    
                    
    型號(hào)下載 訂購功能描述制造商 上傳企業(yè)LOGO
    
                    
    DS90CF384MTD
    3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
    文件：344.12 Kbytes 頁數(shù)：20 Pages
    NSC
    國(guó)半
    

    DS90CF384MTD/NOPB
    絲?。?strong>DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
    
General Description
The DS90C383 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bit
    文件：811.57 Kbytes 頁數(shù)：30 Pages
    TI
    德州儀器
    

    DS90CF384MTD/NOPB.B
    絲?。?strong>DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
    
General Description
The DS90C383 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bit
    文件：811.57 Kbytes 頁數(shù)：30 Pages
    TI
    德州儀器
    

    DS90CF384MTDSLASHNOPB
    絲?。?strong>DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
    
General Description
The DS90C383 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bit
    文件：811.57 Kbytes 頁數(shù)：30 Pages
    TI
    德州儀器
    

    DS90CF384MTDSLASHNOPB.B
    絲?。?strong>DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
    
General Description
The DS90C383 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bit
    文件：811.57 Kbytes 頁數(shù)：30 Pages
    TI
    德州儀器
    

    DS90CF384MTDX/NOPB
    絲?。?strong>DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
    
General Description
The DS90C383 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bit
    文件：811.57 Kbytes 頁數(shù)：30 Pages
    TI
    德州儀器
    

    DS90CF384MTDX/NOPB.B
    絲?。?strong>DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
    
General Description
The DS90C383 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bit
    文件：811.57 Kbytes 頁數(shù)：30 Pages
    TI
    德州儀器
    

    DS90CF384MTDXSLASHNOPB
    絲?。?strong>DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
    
General Description
The DS90C383 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bit
    文件：811.57 Kbytes 頁數(shù)：30 Pages
    TI
    德州儀器
    

    DS90CF384MTDXSLASHNOPB.B
    絲?。?strong>DS90CF384MTD；Package：TSSOP；DS90C383/DS90CF384 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
    
General Description
The DS90C383 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bit
    文件：811.57 Kbytes 頁數(shù)：30 Pages
    TI
    德州儀器
    

    DS90CF384MTD/NOPB
    3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
    文件：410.45 Kbytes 頁數(shù)：22 Pages
    TI
    德州儀器
    

    
            
    
		
        
    
            
    
                
    詳細(xì)參數(shù)
    
            
    
            
      
            	
    • 型號(hào)：
      DS90CF384MTD
    • 功能描述：
      LVDS 接口集成電路 
    • RoHS：
      否 
    • 制造商：
      Texas Instruments 
    • 激勵(lì)器數(shù)量：
      4 
    • 接收機(jī)數(shù)量：
      4 
    • 數(shù)據(jù)速率：
      155.5 Mbps 
    • 工作電源電壓：
      5 V 
    • 最大功率耗散：
      1025 mW 
    • 最大工作溫度：
      + 85 C 
    • 封裝/箱體：
      SOIC-16 Narrow 
    • 封裝：
      Reel 
    
            
    
        
    
            
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            更新時(shí)間2026-1-22 15:29:00
        
    
        
    
          
    
            
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