DS32EL0421 , DS32ELX0421 125 - 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface

文件：2.46088 Mbytes 頁(yè)數(shù)：32 Pages

TI

德州儀器

5-bit DDR LVDS Parallel Data Interface

文件：2.40812 Mbytes 頁(yè)數(shù)：32 Pages

TI

德州儀器

125 - 312.5 MHz Serializer with DDR LVDS Parallel LVDS Interface

文件：522.85 Kbytes 頁(yè)數(shù)：26 Pages

NSC

國(guó)半

125 - 312.5 MHz Serializer with DDR LVDS Parallel LVDS Interface

文件：536.27 Kbytes 頁(yè)數(shù)：26 Pages

NSC

國(guó)半

125-312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface

文件：1.32593 Mbytes 頁(yè)數(shù)：28 Pages

NSC

國(guó)半

具有 DDR LVDS 并行接口的 125MHz 至 312.5MHz FPGA-Link 串行器

The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interfa ? 5-bit DDR LVDS Parallel Data Interface\n? Configurable Output Levels (VOD)\n? Selectable Data Scrambler\n? On Chip LC VCOs\n? Data Valid Signaling to Assist with Synchronization of Multiple Receivers\n? Integrated CML and LVDS Terminations\n? Programmable Output Termination (50? or 75?).\n? Loss o;

TI

德州儀器

5-bit DDR LVDS Parallel Data Interface

文件：2.40812 Mbytes 頁(yè)數(shù)：32 Pages

TI

德州儀器

5-bit DDR LVDS Parallel Data Interface

文件：2.40812 Mbytes 頁(yè)數(shù)：32 Pages

TI

德州儀器

DS32EL0421 , DS32ELX0421 125 - 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface

文件：2.46088 Mbytes 頁(yè)數(shù)：32 Pages

TI

德州儀器

DS32EL0421 , DS32ELX0421 125 - 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface

文件：2.46088 Mbytes 頁(yè)數(shù)：32 Pages

TI

德州儀器