5V E1/T1/J1 Line Interface Unit

文件：1.12939 Mbytes 頁數(shù)：73 Pages

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5V E1/T1/J1 Line Interface Unit

文件：1.12939 Mbytes 頁數(shù)：73 Pages

MAXIM

美信

5V E1/T1/J1 Line Interface Unit

文件：1.12939 Mbytes 頁數(shù)：73 Pages

MAXIM

美信

5V E1/T1/J1 Line Interface Unit

文件：1.12939 Mbytes 頁數(shù)：73 Pages

MAXIM

美信

5V E1/T1/J1 Line Interface Unit

文件：1.12939 Mbytes 頁數(shù)：73 Pages

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T1/J1 Line Interface Unit Design Kit

文件：506.67 Kbytes 頁數(shù)：14 Pages

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E1控制器

The DS2143 is a comprehensive, software-driven E1 framer. It is meant to act as a slave or coprocessor to a microcontroller or microprocessor. Quick access through the parallel control port allows a single micro to handle many E1 lines. The DS2143 is very flexible and can be configured into numerous \n? E1/ISDN-PRI framing transceiver \n? Frames to CAS, CCS, and CRC4 formats \n? Parallel control port \n? On-board two frame elastic-store slip buffer \n? Extracts and inserts CAS signaling bits \n? Programmable output clocks for fractional E1 links, DS0 loopbacks, and drop and insert applications ;

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E1控制器

The DS2143 is a comprehensive, software-driven E1 framer. It is meant to act as a slave or coprocessor to a microcontroller or microprocessor. Quick access through the parallel control port allows a single micro to handle many E1 lines. The DS2143 is very flexible and can be configured into numerous \n? E1/ISDN-PRI framing transceiver \n? Frames to CAS, CCS, and CRC4 formats \n? Parallel control port \n? On-board two frame elastic-store slip buffer \n? Extracts and inserts CAS signaling bits \n? Programmable output clocks for fractional E1 links, DS0 loopbacks, and drop and insert applications ;

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3.3V、E1/T1/J1四線路接口

DS21448是一款四端口E1或T1線路接口單元(LIU)，適用于短程和遠(yuǎn)程應(yīng)用。它將四個獨立的發(fā)送器與四個獨立的接收器整合到一片144引腳PBGA或128引腳LQFP封裝內(nèi)。發(fā)送驅(qū)動器可在75Ω或120Ω應(yīng)用中產(chǎn)生滿足G.703 E1要求的波形，對于T1應(yīng)用提供0dB、-7.5dB、-15dB和-22.5dB的DSX-1或CSU線路補償。 \n? 四個完整的E1、T1或J1 LIU \n? 支持長距離與短距離主干線 \n? 內(nèi)部軟件可選接收側(cè)終端，以用于75Ω/100Ω/120Ω \n? 3.3V電源供電 \n? 32位或128位晶體抖動衰減器，在E1與T1應(yīng)用中僅需一個2.048MHz MCLK，在T1應(yīng)用中也可以選擇采用1.544MHz MCLK \n? 對于E1，產(chǎn)生有或沒有回波損耗的線路補償，對于T1，產(chǎn)生DSX-1與CSU線路補償 \n? AMI、HDB3與B8ZS編碼/解碼 \n? 16.384MHz、8.192MHz、4.096MHz或2.048MHz時鐘輸出合成自恢復(fù)時鐘 \n? 接收器可編程監(jiān)視器模式 \n? ;

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Package：40-DIP（0.600"，15.24mm）；包裝：托盤 功能：- 類別：集成電路（IC） 電信 描述：IC TELECOM INTERFACE 40DIP

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