SBR 肖特基二極管

Yint

音特電子

包裝：散裝 類別：標(biāo)簽，標(biāo)志，護欄，標(biāo)識 標(biāo)簽，貼紙，貼標(biāo) - 空白 描述：LABEL COMP NON-ADH

PANDUIT

類別：焊接，拆焊，返修產(chǎn)品 焊接，拆焊，返修尖頭，噴嘴 描述：TIP DESOLDERING

ATG

包裝：散裝 類別：標(biāo)簽，標(biāo)志，護欄，標(biāo)識 標(biāo)簽，貼紙，貼標(biāo) - 空白 描述：LABEL COMP NON-ADH

PANDUIT

5-Tap Economy Timing Element (Delay Line) All-Silicon Timing Circuit

GENERAL DESCRIPTION The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These devices are offered in surface-mount packages to save PCB area. Low cost and superior reliability over hybrid technology is achieved by the combination of a 100 silicon dela

文件：136.49 Kbytes 頁數(shù)：6 Pages

MAXIM

美信

5-Tap Economy Timing Element Delay Line

DESCRIPTION The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These devices are offered in 8-pin DIPs and surface-mount packages to save PC board area. Low cost and superior reliability over hybrid technology is achieved by the combination of a 100 si

文件：154.6 Kbytes 頁數(shù)：6 Pages

DALLAS

5-Tap Economy Timing Element (Delay Line) All-Silicon Timing Circuit

GENERAL DESCRIPTION The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These devices are offered in surface-mount packages to save PCB area. Low cost and superior reliability over hybrid technology is achieved by the combination of a 100 silicon dela

文件：136.49 Kbytes 頁數(shù)：6 Pages

MAXIM

美信

5-Tap Economy Timing Element Delay Line

DESCRIPTION The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These devices are offered in 8-pin DIPs and surface-mount packages to save PC board area. Low cost and superior reliability over hybrid technology is achieved by the combination of a 100 si

文件：154.6 Kbytes 頁數(shù)：6 Pages

DALLAS

5-Tap Economy Timing Element Delay Line

DESCRIPTION The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These devices are offered in 8-pin DIPs and surface-mount packages to save PC board area. Low cost and superior reliability over hybrid technology is achieved by the combination of a 100 si

文件：154.6 Kbytes 頁數(shù)：6 Pages

DALLAS

5-Tap Economy Timing Element Delay Line

DESCRIPTION The DS1100 series delay lines have five equally spaced taps providing delays from 4ns to 500ns. These devices are offered in 8-pin DIPs and surface-mount packages to save PC board area. Low cost and superior reliability over hybrid technology is achieved by the combination of a 100 si

文件：154.6 Kbytes 頁數(shù)：6 Pages

DALLAS