| 型號(hào) | 下載 訂購(gòu) | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
DRA821 Jacinto? Processors 1 Features Processor cores: ? Dual 64-bit Arm? Cortex?-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex?- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core ? 4× Arm? Cortex?-R5F MCUs at up to 1.0 GHz with optional lockstep oper 文件：4.57573 Mbytes 頁(yè)數(shù)：253 Pages | TI 德州儀器 | TI | ||
DRA821 Jacinto? Processors 1 Features Processor cores: ? Dual 64-bit Arm? Cortex?-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex?- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core ? 4× Arm? Cortex?-R5F MCUs at up to 1.0 GHz with optional lockstep oper 文件：4.45374 Mbytes 頁(yè)數(shù)：252 Pages | TI 德州儀器 | TI | ||
DRA821 Jacinto? Processors 1 Features Processor cores: ? Dual 64-bit Arm? Cortex?-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex?- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core ? 4× Arm? Cortex?-R5F MCUs at up to 1.0 GHz with optional lockstep oper 文件：4.57573 Mbytes 頁(yè)數(shù)：253 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/dra821u4tcbalmq1/marking.html">DRA821U4TCBALMQ1；Package：FCBGA；DRA821 Jacinto? Processors 1 Features Processor cores: ? Dual 64-bit Arm? Cortex?-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex?- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core ? 4× Arm? Cortex?-R5F MCUs at up to 1.0 GHz with optional lockstep oper 文件：4.57573 Mbytes 頁(yè)數(shù)：253 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/dra821u4tcbalmq1/marking.html">DRA821U4TCBALMQ1；Package：FCBGA；DRA821 Jacinto? Processors 1 Features Processor cores: ? Dual 64-bit Arm? Cortex?-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex?- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core ? 4× Arm? Cortex?-R5F MCUs at up to 1.0 GHz with optional lockstep oper 文件：4.45374 Mbytes 頁(yè)數(shù)：252 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/dra821u4tcbalmq1/marking.html">DRA821U4TCBALMQ1；Package：FCBGA；DRA821 Jacinto? Processors 1 Features Processor cores: ? Dual 64-bit Arm? Cortex?-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex?- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core ? 4× Arm? Cortex?-R5F MCUs at up to 1.0 GHz with optional lockstep oper 文件：4.48888 Mbytes 頁(yè)數(shù)：254 Pages | TI 德州儀器 | TI | ||
絲印：DRA821U4TCBALMQ1；Package：FCBGA；DRA821 Jacinto? Processors 1 Features Processor cores: ? Dual 64-bit Arm? Cortex?-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex?- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core ? 4× Arm? Cortex?-R5F MCUs at up to 1.0 GHz with optional lockstep oper 文件：4.48888 Mbytes 頁(yè)數(shù)：254 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/dra821u4tcbalmq1/marking.html">DRA821U4TCBALMQ1；Package：FCBGA；DRA821 Jacinto? Processors 1 Features Processor cores: ? Dual 64-bit Arm? Cortex?-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex?- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core ? 4× Arm? Cortex?-R5F MCUs at up to 1.0 GHz with optional lockstep oper 文件：4.45374 Mbytes 頁(yè)數(shù)：252 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/dra821u4tcbalmq1/marking.html">DRA821U4TCBALMQ1；Package：FCBGA；DRA821 Jacinto? Processors 1 Features Processor cores: ? Dual 64-bit Arm? Cortex?-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex?- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core ? 4× Arm? Cortex?-R5F MCUs at up to 1.0 GHz with optional lockstep oper 文件：4.57573 Mbytes 頁(yè)數(shù)：253 Pages | TI 德州儀器 | TI | ||
絲印：DRA821U4TGBALM；Package：FCBGA；DRA821 Jacinto? Processors 1 Features Processor cores: ? Dual 64-bit Arm? Cortex?-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS – 1MB L2 shared cache per dual-core Cortex?- A72 cluster – 32KB L1 DCache and 48KB L1 ICache per A72 core ? 4× Arm? Cortex?-R5F MCUs at up to 1.0 GHz with optional lockstep oper 文件：4.57573 Mbytes 頁(yè)數(shù)：253 Pages | TI 德州儀器 | TI |
晶體管資料
- 型號(hào)：
- 別名：
三極管、晶體管、晶體三極管
- 生產(chǎn)廠家：
- 制作材料：
50HZ－Thy
- 性質(zhì)：
- 封裝形式：
直插封裝
- 極限工作電壓：
600V
- 最大電流允許值：
8A
- 最大工作頻率：
<1MHZ或未知
- 引腳數(shù)：
3
- 可代換的型號(hào)：
TAG680-...,TIC122-...,TIC126-...,
- 最大耗散功率：
- 放大倍數(shù)：
- 圖片代號(hào)：
B-10
- vtest：
600
- htest：
999900
- atest：
8
- wtest：
0
技術(shù)參數(shù)
- Arm MHz (Max.)：
11001000800
- DRAM：
DDR3L-1600DDR4-1600LPDDR4-1333
- Co-processor(s)：
Arm Cortex-R5F PRU-ICSS
- EMIF：
1x 39-bit with ECC
- Other on-chip memory：
2.5 MB
- Ethernet MAC：
10/100/10006-Port 10/100/1000 PRU EMAC
- Serial I/O：
CAN-FDI2CSPIUARTUSB
- Storage interface：
1x SDIO 4b1x SDIO 8b1x UHSI 4b1x eMMC 8b
- PCIe：
2 PCIe Gen3
- McASP：
3
- Security enabler：
Cryptographic accelerationDebug securityDevice identitySecure bootTrusted execution environment
- USB：
1 USB2.01 USB3.0
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
TI |
25+ |
FCBGA (ALF) |
6000 |
原廠原裝,價(jià)格優(yōu)勢(shì) |
詢價(jià) | ||
TI |
21+正納原裝現(xiàn)貨 |
FCBGA-827 |
100 |
十年以上分銷商原裝進(jìn)口件服務(wù)型 |
詢價(jià) | ||
====無(wú)==== |
24+ |
NA |
10000 |
詢價(jià) | |||
TI |
23+ |
FCBGA |
5000 |
全新原裝正品現(xiàn)貨 |
詢價(jià) | ||
TI德州儀器 |
22+ |
24000 |
原裝正品現(xiàn)貨,實(shí)單可談,量大價(jià)優(yōu) |
詢價(jià) | |||
TI |
25+ |
30000 |
原裝現(xiàn)貨,支持實(shí)單 |
詢價(jià) | |||
24+ |
N/A |
51000 |
一級(jí)代理-主營(yíng)優(yōu)勢(shì)-實(shí)惠價(jià)格-不悔選擇 |
詢價(jià) | |||
Texas Instruments |
25+ |
827-BFBGA FCBGA |
9350 |
獨(dú)立分銷商 公司只做原裝 誠(chéng)心經(jīng)營(yíng) 免費(fèi)試樣正品保證 |
詢價(jià) | ||
TI/德州儀器 |
24+ |
FCBGA |
2500 |
原裝正品現(xiàn)貨,假一罰十 |
詢價(jià) | ||
TI/德州儀器 |
25+ |
原廠封裝 |
10280 |
原廠授權(quán)代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源！ |
詢價(jià) |
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