Triple 3-Input NOR Gate

General Description This device contains three independent gates each of which performs the logic NOR function.

文件：46.09 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導體

TRIPLE 3-INPUT NOR GATES

文件：58 Kbytes 頁數(shù)：2 Pages

NSC

國半

Triple 3-Input NOR Gate

ONSEMI

安森美半導體

TRIPLE 3-INPUT NOR GATES

TI

德州儀器

8-Bit Register with Clear

General Description The DM74LS273 is a high speed 8-bit register, consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch row spacing. Features ■ Edge-triggered ■ 8-bit high speed regi

文件：66.92 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導體

8-Bit Register with Clear

General Description The DM74LS273 is a high speed 8-bit register, consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch row spacing. Features ■ Edge-triggered ■ 8-bit high speed regi

文件：66.92 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導體

8-Bit Register with Clear

General Description The DM74LS273 is a high speed 8-bit register, consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch row spacing. Features ■ Edge-triggered ■ 8-bit high speed regi

文件：66.92 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導體

8-Bit Register with Clear

General Description The DM74LS273 is a high speed 8-bit register, consisting of eight D-type flip-flops with a common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch row spacing. Features ■ Edge-triggered ■ 8-bit high speed regi

文件：66.92 Kbytes 頁數(shù)：6 Pages

FAIRCHILD

仙童半導體

Quad S-R Latch

General Description The DM74LS279 consists of four individual and independent Set-Reset Latches with active low inputs. Two of the four latches have an additional Sinput ANDed with the primary Sinput. A LOW on any Sinput while the Rinput is HIGH will be stored in the latch and appear on the corre

文件：47.44 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導體

Quad S-R Latch

General Description The DM74LS279 consists of four individual and independent Set-Reset Latches with active low inputs. Two of the four latches have an additional Sinput ANDed with the primary Sinput. A LOW on any Sinput while the Rinput is HIGH will be stored in the latch and appear on the corre

文件：47.44 Kbytes 頁數(shù)：4 Pages

FAIRCHILD

仙童半導體