Data Selectors/Multiplexers

General Description These data selectors/multiplexers contain full on-chip decoding to select the desired data source. The DM74150 selects one-of-sixteen data sources. The DM74150 has a strobe input which must be at a LOW logic level to enable these devices. A HIGH level at the strobe forces th

文件：47.42 Kbytes 頁(yè)數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

Quad 2-Line to 1-Line Data Selectors/Multiplexer

General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. Features ■Buffered

文件：39.05 Kbytes 頁(yè)數(shù)：3 Pages

FAIRCHILD

仙童半導(dǎo)體

Quad 2-Line to 1-Line Data Selectors/Multiplexer

General Description These data selectors/multiplexers contain inverters and drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word is selected from one of two sources and is routed to the four outputs. Features ■Buffered

文件：39.05 Kbytes 頁(yè)數(shù)：3 Pages

FAIRCHILD

仙童半導(dǎo)體

Hex Inverting Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent gates each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.

文件：35.58 Kbytes 頁(yè)數(shù)：3 Pages

FAIRCHILD

仙童半導(dǎo)體

8-Bit Serial In/Parallel Out Shift Registers

General Description These 8-bit shift registers feature gated serial inputs and n asynchronous clear. A LOW logic level at either serial input inhibits entry of the new data, and resets the first flip-flop to the LOW level at the next clock pulse, thus providing complete control over incoming d

文件：48.83 Kbytes 頁(yè)數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

8-Bit Parallel-to-Serial Converter

General Description The ’165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputting occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new da

文件：109.14 Kbytes 頁(yè)數(shù)：6 Pages

NSC

國(guó)半

8-Bit Parallel-to-Serial Converter

General Description The ’165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputting occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new da

文件：109.14 Kbytes 頁(yè)數(shù)：6 Pages

NSC

國(guó)半

Hex Buffers with High Voltage Open-Collector Outputs

General Description This device contains six independent gates each of which performs a buffer function. The open-collector outputs require external pull-up resistors for proper logical operation.

文件：47.58 Kbytes 頁(yè)數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

Hex/Quad D-Type Flip-Flop with Clear

文件：42.93 Kbytes 頁(yè)數(shù)：4 Pages

FAIRCHILD

仙童半導(dǎo)體

Hex/Quad D Flip-Flops with Clear

文件：308.47 Kbytes 頁(yè)數(shù)：8 Pages

FAIRCHILD

仙童半導(dǎo)體