Kingston DDR3/3L DRAM for embedded applications

KEY FEATURES ? Double Data Rate (DDR) architecture: two data transfers per clock cycle ? High-speed data transfer is realized by 8 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver

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KINGSTON

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Kingston i-Temp DDR3/3L DRAM for embedded applications

KEY FEATURES ? Double Data Rate architecture: two data transfers per clock cycle ? High-speed data transfer is realized by 8 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver ? DOS

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KINGSTON

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DDR3/3L DRAM for embedded applications

? Double-data-rate architecture: two data transfers per clock cycle\r\n? The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture\r\n? Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver\r\n? DOS is;

Kingston

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DRAM Components

Kingston

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