Hammers - Compact Hammers - 26 mm Heavy Duty SDS-Plus Combination

D25114K Features Ideal for drilling anchor and fixing holes into concrete and masonry from 4 to 26 mm in diameter Electronic variable speed for total control in any application Rotation-stop for light chiselling applications in brick, soft masonry and occasionally concrete Impact-stop for

文件：61.86 Kbytes 頁數(shù)：1 Pages

DEWALT

1.5 m m D2500-Type Digital Isolated DFB Laser Module

Description The D2500-Type Digital Isolated DFB Laser Module contains an internally cooled, InGaAsP, MQW, distributed-feedback (DFB) laser designed for 1.5 μm applications. The laser is designed to be used in OC-12/ STM-4 (622 Mbits/s) and OC-48/STM-16 (2.488 Gbits/ s) for long-reach and extende

文件：267.51 Kbytes 頁數(shù)：8 Pages

AGERE

1.5 m m D2500-Type Digital Isolated DFB Laser Module

Description The D2500-Type Digital Isolated DFB Laser Module contains an internally cooled, InGaAsP, MQW, distributed-feedback (DFB) laser designed for 1.5 μm applications. The laser is designed to be used in OC-12/ STM-4 (622 Mbits/s) and OC-48/STM-16 (2.488 Gbits/ s) for long-reach and extende

文件：267.51 Kbytes 頁數(shù)：8 Pages

AGERE

4G bist DDR3L SDRAM

Features * Doubledatarate archiectne Wo datatranslers perclodk oyoe * Thehghspesd data tanster isiealzed by he 8 bts preletch ppeined achiectue * BKdectonal diflerontal data stobe (0QS and /DQ8) s tanemitedheceted WMh data for captuing data 不 the receiver * DQSisedgeaigned wih dataforREADs

文件：1.80575 Mbytes 頁數(shù)：25 Pages

KINGSTON

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Kingston DDR3/3L DRAM for embedded applications

KEY FEATURES ? Double Data Rate (DDR) architecture: two data transfers per clock cycle ? High-speed data transfer is realized by 8 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：3.59565 Mbytes 頁數(shù)：2 Pages

KINGSTON

金士頓

Kingston i-Temp DDR3/3L DRAM for embedded applications

KEY FEATURES ? Double Data Rate architecture: two data transfers per clock cycle ? High-speed data transfer is realized by 8 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver ? DOS

文件：425.79 Kbytes 頁數(shù)：2 Pages

KINGSTON

金士頓

Kingston i-Temp DDR3/3L DRAM for embedded applications

KEY FEATURES ? Double Data Rate architecture: two data transfers per clock cycle ? High-speed data transfer is realized by 8 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver ? DOS

文件：425.79 Kbytes 頁數(shù)：2 Pages

KINGSTON

金士頓

Kingston DDR3/3L DRAM for embedded applications

KEY FEATURES ? Double Data Rate (DDR) architecture: two data transfers per clock cycle ? High-speed data transfer is realized by 8 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：3.59565 Mbytes 頁數(shù)：2 Pages

KINGSTON

金士頓

Kingston DDR3/3L DRAM for embedded applications

KEY FEATURES ? Double Data Rate (DDR) architecture: two data transfers per clock cycle ? High-speed data transfer is realized by 8 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver

文件：3.59565 Mbytes 頁數(shù)：2 Pages

KINGSTON

金士頓

Kingston i-Temp DDR3/3L DRAM for embedded applications

KEY FEATURES ? Double Data Rate architecture: two data transfers per clock cycle ? High-speed data transfer is realized by 8 bits prefetch pipelined architecture ? Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for capturing data at the receiver ? DOS

文件：425.79 Kbytes 頁數(shù)：2 Pages

KINGSTON

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