1.8V PLL Differential 1:10 SDRAM Clock Driver

Renesas

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Package：56-TFBGA；包裝：托盤 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：IC PLL CLK DVR SDRAM 56-CABGA

Renesas Electronics America Inc

Package：56-TFBGA；包裝：托盤 類別：集成電路（IC） 應(yīng)用特定時鐘/定時 描述：IC PLL CLK DVR SDRAM 56-CABGA

Renesas Electronics America Inc

1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

FEATURES: ? 1 to 10 differential clock distribution ? Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications ? Operating frequency: 125MHz to 340MHz ? Very low skew: ≤40ps ? Very low jitter: ≤40ps ? 1.8V AVDD and 1.8V VDDQ ? CMOS control signal input ? Test mode en

文件：292.2 Kbytes 頁數(shù)：14 Pages

RENESAS

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1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

FEATURES: ? 1 to 10 differential clock distribution ? Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications ? Operating frequency: 125MHz to 410MHz ? Stabilization time:

文件：292.57 Kbytes 頁數(shù)：14 Pages

RENESAS

瑞薩

1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

FEATURES: ? 1 to 10 differential clock distribution ? Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications ? Operating frequency: 125MHz to 410MHz ? Stabilization time:

文件：318.27 Kbytes 頁數(shù)：15 Pages

RENESAS

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