2.5V Phase Locked Loop Differential 1:10 SDRAM Clock Driver

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2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

DESCRIPTION: The CSPT857C is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9],Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, F

文件：348.05 Kbytes 頁數(shù)：16 Pages

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2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

FEATURES: ? 1 to 10 differential clock distribution ? Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications requiring improved output crosspoint voltage ? Operating frequency: 60MHz to 220MHz ? Very low skew: –

文件：347.57 Kbytes 頁數(shù)：16 Pages

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CX857 IC

文件：137.2 Kbytes 頁數(shù)：2 Pages

SONYSony Corporation

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