CDCVF310集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器規(guī)格書PDF中文資料

CDCVF310屬于集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器。由德州儀器制造生產(chǎn)的CDCVF310時(shí)鐘緩沖器，驅(qū)動(dòng)器時(shí)鐘緩沖器和驅(qū)動(dòng)器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號(hào)在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號(hào)，以同步系統(tǒng)內(nèi)的活動(dòng)。盡管這些器件最常用到的功能就是緩沖（即，為使信號(hào)不受驅(qū)動(dòng)負(fù)載的影響而從某個(gè)信號(hào)源復(fù)制信號(hào)），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號(hào)路徑、按某個(gè)整數(shù)值分割信號(hào)頻率，或進(jìn)行所用電信號(hào)格式轉(zhuǎn)換。

1FEATURES

· High-Performance 1:10 Clock Driver

· Pin-to-Pin Skew < 100 ps at VDD 3.3 V

· VDD Range = 2.3 V to 3.6 V

· Input Clock Up To 200 MHz (See Figure 7)

· Operating Temperature Range –40°C to 85°C

· Output Enable Glitch Suppression

· Distributes One Clock Input to Two Banks of

Five Outputs

· Packaged in 24-Pin TSSOP

· Pin-to-Pin Compatible to the CDCVF2310,

Except the R = 22-Ω Series Damping

Resistors at Yn

APPLICATIONS

· General-Purpose Applications

DESCRIPTION

The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five

outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless

of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a

low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on

the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins

(1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a

2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable

sequence to distribute full period clock signals.

The CDCVF310 is characterized for operation from –40C to 85C.