3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：144.16 Kbytes 頁數(shù)：11 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：764.4 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：766.76 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

適用于 DRAM 應(yīng)用且具有 10 個輸出的 3.3V 鎖相環(huán)路時鐘驅(qū)動器

The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The ? Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1\n? Operating Frequency 50 MHz to 175 MHz\n? Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps\n? Available in Plastic 24-Pin TSSOP\n? Distributes One Clock Input to One Bank of 10 Outputs\n? 25- On-Chip Series Damping ;

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：766.76 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：764.4 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes 頁數(shù)：18 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：166.43 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：551.76 Kbytes 頁數(shù)：17 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

文件：557.49 Kbytes 頁數(shù)：18 Pages

TI

德州儀器