2.5-V PHASE-LOCK LOOP CLOCK DRIVER

文件：769.76 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

文件：771.55 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

文件：771.55 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

文件：769.76 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

文件：769.76 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

文件：277.68 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

文件：771.55 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

文件：769.76 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

文件：771.55 Kbytes 頁數(shù)：16 Pages

TI

德州儀器

2.5V 鎖相環(huán) DDR 時鐘驅(qū)動器

The CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by th ·Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications\n ·Spread Spectrum Clock Compatible\n ·Operating Frequency: 60 MHz to 200 MHz\n ·Low Jitter (cycle-cycle): ±50 ps\n ·Low Static Phase Offset: ±50 ps\n ·Low Jitter (Period): ±35 ps\n ·Distributes One Differential Clock I;

TI

德州儀器