2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2 LINE SERIAL INTERFACE

文件：228.24 Kbytes 頁數(shù)：15 Pages

TI

德州儀器

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE

文件：805.15 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

2.5V 鎖相環(huán)差動時鐘驅(qū)動器，具有 2 線路串行接口

The CDCV850 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by th ·Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications\n ·Spread Spectrum Clock Compatible\n ·Operating Frequency: 60 to 140 MHz\n ·Low Jitter (cyc.cyc): ±75 ps\n ·Distributes One Differential Clock Input to Ten Differential Outputs\n ·Two-Line Serial Interface Provides Out;

TI

德州儀器

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE

文件：805.15 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE

文件：805.15 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE

文件：805.15 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE

文件：805.15 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2 LINE SERIAL INTERFACE

文件：228.24 Kbytes 頁數(shù)：15 Pages

TI

德州儀器

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE

文件：805.15 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE

文件：805.15 Kbytes 頁數(shù)：20 Pages

TI

德州儀器