1.8-V PHASE LOCK LOOP CLOCK DRIVER

文件：485.53 Kbytes 頁(yè)數(shù)：17 Pages

SEME-LAB

1.8-V PHASE LOCK LOOP CLOCK DRIVER

文件：485.53 Kbytes 頁(yè)數(shù)：17 Pages

SEME-LAB

1.8-V PHASE LOCK LOOP CLOCK DRIVER

文件：485.53 Kbytes 頁(yè)數(shù)：17 Pages

SEME-LAB

用于 DDR2 SDRAM 應(yīng)用的 1.8V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器

The CDCU877B is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock inputpair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the inpu ·1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications\n·Spread Spectrum Clock Compatible\n·Operating Frequency: 10 MHz to 340 MHz\n·Low Current Consumption: FBIN) are Used to Synchronize the Outputs to the Input Clocks\n·Fail-Safe Inputs\nMicroStar is a trademark of Texas In;

TI

德州儀器

1.8-V PHASE LOCK LOOP CLOCK DRIVER

TT Electronics

Package：52-VFBGA；包裝：管件 類別：集成電路（IC） 應(yīng)用特定時(shí)鐘/定時(shí) 描述：IC PLL CLOCK DRIVER 1.8V 52-BGA

TI

德州儀器

Package：52-VFBGA；包裝：散裝 類別：集成電路（IC） 應(yīng)用特定時(shí)鐘/定時(shí) 描述：IC PLL CLOCK DRIVER 1.8V 52-BGA

TI

德州儀器