絲?。?strong>CDCLVD1212；Package：VQFN(RHA)；CDCLVD1212 2:12 Low Additive Jitter LVDS Buffer

1 Features 1? 2:12 Differential Buffer ? Low Additive Jitter:

文件：1.1005 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

絲?。?strong>CDCLVD1212；Package：VQFN(RHA)；CDCLVD1212 2:12 Low Additive Jitter LVDS Buffer

1 Features 1? 2:12 Differential Buffer ? Low Additive Jitter:

文件：1.1005 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

絲?。?strong>CDCLVD1212；Package：VQFN(RHA)；CDCLVD1212 2:12 Low Additive Jitter LVDS Buffer

1 Features 1? 2:12 Differential Buffer ? Low Additive Jitter:

文件：1.1005 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

絲印：CDCLVD1212；Package：VQFN；CDCLVD1212 2:12 Low Additive Jitter LVDS Buffer

1 Features 1? 2:12 Differential Buffer ? Low Additive Jitter:

文件：1.10018 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

低抖動(dòng) 2 路輸入可選 1:12 通用至 LVDS 緩沖器

The CDCLVD1212 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11) with minimum skew for clock distribution. The CDCLVD1212 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, ? 2:12 Differential Buffer\n? Low Output Skew of 35 ps (Maximum)\n? Selectable Clock Inputs Through Control Pin\n? Clock Frequency: Up to 800 MHz\n? LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs\n? Packaged in 6-mm × 6-mm, 40-Pin VQFN (RHA)\n? ESD Protection Exceeds 3-kV H;

TI

德州儀器

CDCLVD1212 2:12 Low Additive Jitter LVDS Buffer

1 Features 1? 2:12 Differential Buffer ? Low Additive Jitter:

文件：1.1005 Mbytes 頁數(shù)：23 Pages

TI

德州儀器

2:12 Low Additive Jitter LVDS Buffer

文件：707.95 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

2:12 Low Additive Jitter LVDS Buffer

文件：707.95 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

包裝：散裝 功能：時(shí)鐘緩沖器/驅(qū)動(dòng)器/接收器/轉(zhuǎn)換器 類別：開發(fā)板，套件，編程器 評(píng)估和演示板及套件 描述：EVAL MODULE FOR CDCLVD1212

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德州儀器

Package：40-VFQFN 裸露焊盤；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 時(shí)鐘緩沖器，驅(qū)動(dòng)器 描述：IC CLK BUFFER 2:12 800MHZ 40VQFN

TI

德州儀器