CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features ? 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations ? 8 hardware output enable (OE#) controls ? Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) ? Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 頁數(shù)：34 Pages

TI

德州儀器

CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5

文件：1.64389 Mbytes 頁數(shù)：31 Pages

TI

德州儀器

用于 PCIe? 第 1 代至第 5 代的 8 輸出時鐘緩沖器，具有可選的 SMBus 地址

CDCDB803 是一款符合 DB800ZL 標(biāo)準(zhǔn)的 8 路輸出 LP-HCSL 時鐘緩沖器，能夠為第 1 代到第 5 代 PCIe、QuickPath Interconnect (QPI)、UPI、SAS 和 SATA 接口分配基準(zhǔn)時鐘。使用 SMBus 接口和 8 輸出使能引腳，可以單獨配置和控制所有 8 個輸出。 CDCDB803 是一款 DB800ZL 衍生緩沖器，符合或超過 DB800ZL 中的系統(tǒng)參數(shù)規(guī)格。它還符合或超過了 DB2000Q 的參數(shù)規(guī)格。 CDCDB803 采用 6mm × 6mm 48 引腳 VQFN 封裝。 ? 具有可編程集成 85?（默認(rèn)值）或 100? 差分輸出終端的 8 個 LP-HCSL 輸出\n? 使用第 5 代 PCIE 濾波器之后的附加相位抖動： \n? 可編程輸出轉(zhuǎn)換率控制 \n? 3.3V 內(nèi)核和 IO 電源電壓\n? 電流消耗：72mA（最大值）\n? 6mm × 6mm 48 引腳 VQFN 封裝;

TI

德州儀器

CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features ? 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations ? 8 hardware output enable (OE#) controls ? Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) ? Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 頁數(shù)：34 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cdcb803/marking.html">CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features ? 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations ? 8 hardware output enable (OE#) controls ? Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) ? Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 頁數(shù)：34 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cdcb803/marking.html">CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features ? 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations ? 8 hardware output enable (OE#) controls ? Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) ? Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 頁數(shù)：34 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cdcb803/marking.html">CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features ? 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations ? 8 hardware output enable (OE#) controls ? Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) ? Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 頁數(shù)：34 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cdcb803/marking.html">CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features ? 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations ? 8 hardware output enable (OE#) controls ? Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) ? Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

文件：1.36342 Mbytes 頁數(shù)：34 Pages

TI

德州儀器

絲印：CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5

文件：1.64389 Mbytes 頁數(shù)：31 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cdcb803/marking.html">CDCB803；Package：VQFN；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5

文件：1.64389 Mbytes 頁數(shù)：31 Pages

TI

德州儀器