CDCDB2000集成電路（IC）的時鐘緩沖器驅動器規(guī)格書PDF中文資料

CDCDB2000屬于集成電路（IC）的時鐘緩沖器驅動器。由德州儀器制造生產的CDCDB2000時鐘緩沖器，驅動器時鐘緩沖器和驅動器集成電路產品族中的產品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時間參考信號，以同步系統(tǒng)內的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅動負載的影響而從某個信號源復制信號），但是該產品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數值分割信號頻率，或進行所用電信號格式轉換。

1 Features

? 20 LP-HCSL outputs with integrated 85-Ω output

terminations

? 8 hardware output enable (OE#) controls

? Additive phase jitter after DB2000QL filter:

< 0.08ps rms

? Supports PCIe Gen 4 and Gen 5 Common Clock

(CC) and Individual Reference (IR) architectures

– Spread spectrum-compatible

? Cycle-to-cycle jitter: < 50 ps

? Output-to-output skew: < 50 ps

? Input-to-output delay: < 3 ns

? 3.3-V core and IO supply voltages

? Hardware-controlled low power mode (PD#)

? Side-Band Interface (SBI) for output control in PD#

mode

? 9 selectable SMBus addresses

? Power consumption: < 600 mW

? 6-mm × 6-mm, 80-pin TLGA/GQFN package

2 Applications

? Microserver & tower server

? Storage area network & host bus adapter card

? Network attached storage

? Hardware accelerator

3 Description

The CDCDB2000 is a 20-output LP-HCSL,

DB2000QL compliant, clock buffer capable of

distributing the reference clock for PCIe Gen 1-5,

QuickPath Interconnect (QPI), UPI, SAS, and SATA

interfaces. The SMBus, SBI, and 8 output enable

pins allow the configuration and control of all 20

outputs individually. The CDCDB2000 is a DB2000QL

derivative buffer and meets or exceeds the system

parameters in the DB2000QL specification. The

CDCDB2000 is packaged in a 6-mm × 6-mm TLGA/

GQFN package with 80 leads.