CDCBT1001 1.2-V to 1.8-V Clock Buffer and Level Translator

1 Features ? Clock frequency range: DC to 24 MHz ? 1.2-V to 1.8-V LVCMOS clock level translation: – VDD_IN = 1.2 V ± 10 – VDD_OUT = 1.8 V ± 10 ? Low additive jitter and phase noise: – 0.8-ps maximum 12-kHz to 5-MHz additive RMS jitter (fout = 24 MHz) – –120-dBc/Hz maximum phase noise at 1-

文件：1.03342 Mbytes 頁數(shù)：19 Pages

TI

德州儀器

CDCBT1001 1.2-V to 1.8-V Clock Buffer and Level Translator

1 Features ? Clock frequency range: DC to 24 MHz ? 1.2-V to 1.8-V LVCMOS clock level translation: – VDD_IN = 1.2 V ± 10% – VDD_OUT = 1.8 V ± 10% ? Low additive jitter and phase noise: – 0.8-ps maximum 12-kHz to 5-MHz additive RMS jitter (fout = 24 MHz) – –120-dBc/Hz maximum phase n

文件：999.75 Kbytes 頁數(shù)：19 Pages

TI

德州儀器

1.2V 至 1.8V 時(shí)鐘緩沖器和電平轉(zhuǎn)換器

? Clock frequency range: DC to 24 MHz\n? VDD_IN = 1.2 V ± 10%\n? Low additive jitter and phase noise: \n? –120-dBc/Hz maximum phase noise at 1-kHz offset (fout = 24 MHz)\n? 5-ns 20% to 80% rise/fall time\n? Low current consumption\n? –40°C to 85°C operating temperature range;

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/bt/marking.html">BT；Package：X2SON；CDCBT1001 1.2-V to 1.8-V Clock Buffer and Level Translator

1 Features ? Clock frequency range: DC to 24 MHz ? 1.2-V to 1.8-V LVCMOS clock level translation: – VDD_IN = 1.2 V ± 10 – VDD_OUT = 1.8 V ± 10 ? Low additive jitter and phase noise: – 0.8-ps maximum 12-kHz to 5-MHz additive RMS jitter (fout = 24 MHz) – –120-dBc/Hz maximum phase noise at 1-

文件：1.03342 Mbytes 頁數(shù)：19 Pages

TI

德州儀器

CDCBT1001 1.2-V to 1.8-V Clock Buffer and Level Translator

1 Features ? Clock frequency range: DC to 24 MHz ? 1.2-V to 1.8-V LVCMOS clock level translation: – VDD_IN = 1.2 V ± 10% – VDD_OUT = 1.8 V ± 10% ? Low additive jitter and phase noise: – 0.8-ps maximum 12-kHz to 5-MHz additive RMS jitter (fout = 24 MHz) – –120-dBc/Hz maximum phase n

文件：999.75 Kbytes 頁數(shù)：19 Pages

TI

德州儀器

CDCBT1001 1.2-V to 1.8-V Clock Buffer and Level Translator

1 Features ? Clock frequency range: DC to 24 MHz ? 1.2-V to 1.8-V LVCMOS clock level translation: – VDD_IN = 1.2 V ± 10% – VDD_OUT = 1.8 V ± 10% ? Low additive jitter and phase noise: – 0.8-ps maximum 12-kHz to 5-MHz additive RMS jitter (fout = 24 MHz) – –120-dBc/Hz maximum phase n

文件：999.75 Kbytes 頁數(shù)：19 Pages

TI

德州儀器

Package：5-XFDFN 裸露焊盤；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 時(shí)鐘緩沖器，驅(qū)動(dòng)器 描述：1.2 TO 1.8-V CLOCK BUFFER AND LE

TI

德州儀器

包裝：盒 功能：時(shí)鐘緩沖器 類別：開發(fā)板，套件，編程器 評估和演示板及套件 描述：EVAL BOARD FOR CDCBT1001

TI

德州儀器