3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：132.48 Kbytes 頁數(shù)：9 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/ck509/marking.html">CK509；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

文件：447.38 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/ck509/marking.html">CK509；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

文件：447.38 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/ck509/marking.html">CK509；Package：TSSOP；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

文件：447.38 Kbytes 頁數(shù)：14 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：612.1 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：612.1 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

Package：24-TSSOP（0.173"，4.40mm 寬）；包裝：托盤 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC 3.3V PLL CLOCK DRVR 24-TSSOP

TI

德州儀器

Package：24-TSSOP（0.173"，4.40mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC 3.3V PLL CLOCK DRVR 24-TSSOP

TI

德州儀器