CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features ? Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter ? Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) ? Adaptive Output Stage Controls Reflection ? Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 頁數：23 Pages

TI

德州儀器

LOW PHASE-NOISE TWO-CHANNEL CLOCK FAN-OUT BUFFER

文件：750.82 Kbytes 頁數：15 Pages

TI

德州儀器

雙通道方波/正弦-方波時鐘緩沖器

CDC3RL02 是一款雙通道時鐘扇出緩沖器，非常適用于需要時鐘緩沖且具有最小附加相位噪聲和扇出功能的便攜式終端設備（如手機）。該器件將溫度補償晶體振蕩器 (TCXO) 等單個主時鐘緩沖至多個外設。該器件具有兩個時鐘請求輸入（CLK_REQ1 和 CLK_REQ2），其中每個輸入均支持單個時鐘輸出。\n\nCDC3RL02 在主時鐘輸入 (MCLK_IN) 處接受方波或正弦波，無需交流耦合電容器?？山邮艿淖钚≌也?0.3V 信號（峰峰值）。CDC3RL02 旨在提供極小的通道間偏差、附加輸出抖動和附加相位噪聲。自適應時鐘輸出緩沖器可在寬電容負荷范圍內提供受控的轉換率，從而更大限度地降低 E ? 低附加噪聲： \n? 10kHz 偏移相位噪聲時為 –149dBc/Hz \n? 0.37ps (RMS) 輸出抖動\n \n? 限制輸出轉換率可降低 EMI（對于 10pF 至 50pF 的負載，上升/下降時間為 1ns 至 5ns）\n? 自適應輸出級控制反射\n? 穩(wěn)壓 1.8V 外部可用 I/O 電源\n? 超小型 8 凸點 YFP 0.4mm 間距 WCSP（0.8mm × 1.6mm）\n? ESD 性能超過 JESD 22 \n? 2000V 人體放電模型 (A114-A)\n? 1000V 帶電器件模型（JESD22-C101-A III 級）;

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/4ln/marking.html">4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features ? Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter ? Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) ? Adaptive Output Stage Controls Reflection ? Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 頁數：23 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/4ln/marking.html">4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features ? Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter ? Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) ? Adaptive Output Stage Controls Reflection ? Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 頁數：23 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/4ln/marking.html">4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features ? Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter ? Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) ? Adaptive Output Stage Controls Reflection ? Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 頁數：23 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/4ln/marking.html">4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features ? Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter ? Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) ? Adaptive Output Stage Controls Reflection ? Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 頁數：23 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/4ln/marking.html">4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features ? Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter ? Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) ? Adaptive Output Stage Controls Reflection ? Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 頁數：23 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/4ln/marking.html">4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features ? Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter ? Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) ? Adaptive Output Stage Controls Reflection ? Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 頁數：23 Pages

TI

德州儀器

Low Phase-Noise Two-Channel Clock Fan-Out Buffer

文件：820.58 Kbytes 頁數：20 Pages

TI

德州儀器