絲?。?a target="_blank" title="Marking" href="/cdc319/marking.html">CDC319；Package：SSOP；1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE

High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM (Synchronous DRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps Pulse Skew, tsk(p), Less Than 500 ps Supports up to Two Unbuffered SDRAM DIMMs (Dual Inline Memory Modules) I2C Serial Interface Provides Individual Ena

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PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 87 x 87 MILS Die Thickness 9.0 MILS Base Bonding Pad Area 24 x 15 MILS Emitter Bonding Pad Area 38 x 16 MILS Top Side Metalization Al - 30,000? Back Side Metalization Ti/Ni/Ag - 11,000?

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