| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
CDC2536 | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On- 文件:348.1 Kbytes 頁數(shù):16 Pages | TI 德州儀器 | TI | |
CDC2536 | 3.3V PHASE-LOCK LOOP CLOCK DRIVER 文件:490.18 Kbytes 頁數(shù):15 Pages | TI 德州儀器 | TI | |
CDC2536 | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS 文件:143.79 Kbytes 頁數(shù):10 Pages | TI 德州儀器 | TI | |
絲印:CDC2536;Package:SSOP;3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On- 文件:348.1 Kbytes 頁數(shù):16 Pages | TI 德州儀器 | TI | ||
絲?。?strong>CDC2536;Package:SSOP;3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On- 文件:348.1 Kbytes 頁數(shù):16 Pages | TI 德州儀器 | TI | ||
絲?。?strong>CDC2536;Package:SSOP;3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS FEATURES · Low Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · On- 文件:348.1 Kbytes 頁數(shù):16 Pages | TI 德州儀器 | TI | ||
CDC2536 | 具有 1/2x、1x 和 2x 頻率選項的 125MHz、3.3V PLL 時鐘驅(qū)動器 The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors op ? Low Output Skew for Clock-Distribution and Clock-Generation Applications\n? Distributes One Clock Input to Six Outputs\n? No External RC Network Required\n? External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input\n? TTL-Compatible Inputs and Outputs\n? State-of-the-Art E; | TI 德州儀器 | TI | |
3.3V PHASE-LOCK LOOP CLOCK DRIVER 文件:490.18 Kbytes 頁數(shù):15 Pages | TI 德州儀器 | TI | ||
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS 文件:143.79 Kbytes 頁數(shù):10 Pages | TI 德州儀器 | TI | ||
3.3V PHASE-LOCK LOOP CLOCK DRIVER 文件:490.18 Kbytes 頁數(shù):15 Pages | TI 德州儀器 | TI |
技術(shù)參數(shù)
- Additive RMS jitter (Typ) (fs):
200
- Output frequency (Max) (MHz):
125
- Number of outputs:
6
- Output supply voltage (V):
3.3
- Core supply voltage (V):
3.3
- Output skew (ps):
500
- Features:
Spread spectrum clocking (SSC)
- Operating temperature range (C):
0 to 70
- Rating:
Catalog
- Output type:
TTL
- Input type:
TTL
| 供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
TI |
25+ |
SSOP |
18000 |
原廠直接發(fā)貨進口原裝 |
詢價 | ||
TMS |
24+ |
SSOP28 |
50 |
詢價 | |||
TI |
01+ |
SSOP28 |
13 |
全新原裝進口自己庫存優(yōu)勢 |
詢價 | ||
TI |
23+ |
SSOP |
5000 |
原裝正品,假一罰十 |
詢價 | ||
TI |
17+ |
SSOP28 |
9988 |
只做原裝進口,自己庫存 |
詢價 | ||
TI/德州儀器 |
24+ |
SSOP |
9600 |
原裝現(xiàn)貨,優(yōu)勢供應,支持實單! |
詢價 | ||
TI/德州儀器 |
23+ |
SSOP28 |
3000 |
一級代理原廠VIP渠道,專注軍工、汽車、醫(yī)療、工業(yè)、 |
詢價 | ||
TI德州儀器 |
22+ |
24000 |
原裝正品現(xiàn)貨,實單可談,量大價優(yōu) |
詢價 | |||
TI |
23+ |
SSOP28 |
20000 |
全新原裝假一賠十 |
詢價 | ||
TI |
23+ |
SSOP |
8000 |
只做原裝現(xiàn)貨 |
詢價 |
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