絲?。?a target="_blank" title="Marking" href="/hct73m/marking.html">HCT73M；Package：SOIC；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 頁數(shù)：24 Pages

TI

德州儀器

CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 頁數(shù)：24 Pages

TI

德州儀器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes 頁數(shù)：18 Pages

TI

德州儀器

SOIC(D)

RENESAS

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上傳：深圳市壹芯創(chuàng)科技有限公司

INTEL(英特爾)

上傳：深圳市盈慧通電子有限公司