絲印：CD74HCT533E；Package：PDIP；High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

Features ? Common Latch-Enable Control ? Common Three-State Output Enable Control ? Buffered Inputs ? Three-State Outputs ? Bus Line Driving Capacity ? Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output) ? Fanout (Over Temperature Range) - Standard Outputs

文件：610.89 Kbytes 頁數(shù)：17 Pages

TI

德州儀器

Octal D-type Transparent Latches (with inverted 3-state outputs)

Description When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high a

文件：121.46 Kbytes 頁數(shù)：9 Pages

RENESAS

瑞薩

Octal D-type Transparent Latches(with inverted 3-state outputs)

Description When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high a

文件：62.86 Kbytes 頁數(shù)：10 Pages

HITACHIHitachi Semiconductor

日立日立公司

Octal D-type Transparent Latches (with inverted 3-state outputs)

Description When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high a

文件：121.46 Kbytes 頁數(shù)：9 Pages

RENESAS

瑞薩