絲?。?a target="_blank" title="Marking" href="/cd74hct280e/marking.html">CD74HCT280E；Package：PDIP；High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker

Features ? Typical Propagation Delay = 17ns at VCC = 5V, CL = 15pF, TA = 25oC ? Replaces LS180 Types ? Easily Cascadable ? Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads ? Wide Op

文件：596.95 Kbytes 頁數(shù)：17 Pages

TI

德州儀器

9-bit odd/even parity generator/checker

GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Word-length easily expanded by cascading ? Similar pin configuration to the “180” for

文件：49.67 Kbytes 頁數(shù)：7 Pages

PHI

PHI

9-bit odd/even parity generator/checker

1. General description The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs ar

文件：245.09 Kbytes 頁數(shù)：13 Pages

NEXPERIA

安世

9-bit odd/even parity generator/checker

GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES ? Word-length easily expanded by cascading ? Similar pin configuration to the “180” for

文件：49.67 Kbytes 頁數(shù)：7 Pages

PHI

PHI