CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 頁數(shù)：24 Pages

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德州儀器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：57.26 Kbytes 頁數(shù)：8 Pages

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德州儀器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.53 Kbytes 頁數(shù)：13 Pages

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德州儀器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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德州儀器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes 頁數(shù)：15 Pages

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Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes 頁數(shù)：18 Pages

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德州儀器

具有復(fù)位功能的高速 CMOS 邏輯雙路負邊沿觸發(fā)式 J-K 觸發(fā)器

The ?HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.\n\n These flip-flops have independent J, K, Reset and Cl ? Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times\n? Complementary Outputs\n? Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C\n? Standard Outputs . . . . . 10 LSTTL Loads\n? Wide Operating Temperature Range . . . –55°C to 125°C\n? Significant Pow;

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德州儀器

絲印：CD74HC73E；Package：PDIP；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 頁數(shù)：24 Pages

TI

德州儀器

絲印：CD74HC73E；Package：PDIP；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 頁數(shù)：24 Pages

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德州儀器

絲?。?a target="_blank" title="Marking" href="/hc73m/marking.html">HC73M；Package：SOIC；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 頁數(shù)：24 Pages

TI

德州儀器