絲?。?strong>CD74ACT10E；Package：PDIP；TRIPLE 3-INPUT POSITIVE-NAND GATES

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：462.81 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

絲?。?strong>CD74ACT10E；Package：PDIP；TRIPLE 3-INPUT POSITIVE-NAND GATES

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：462.81 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

絲印：CD74ACT10E；Package：PDIP；TRIPLE 3-INPUT POSITIVE-NAND GATES

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：462.81 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

絲?。?strong>CD74ACT10E；Package：PDIP；TRIPLE 3-INPUT POSITIVE-NAND GATES

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：462.81 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

Triple 3-Input NAND Gate

文件：29.45 Kbytes 頁數(shù)：5 Pages

TI

德州儀器

TRIPLE 3-INPUT POSITIVE-NAND GATES

文件：806.69 Kbytes 頁數(shù)：12 Pages

TI

德州儀器