CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 頁(yè)數(shù)：24 Pages

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德州儀器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.53 Kbytes 頁(yè)數(shù)：13 Pages

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德州儀器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes 頁(yè)數(shù)：15 Pages

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德州儀器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：452.31 Kbytes 頁(yè)數(shù)：15 Pages

TI

德州儀器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes 頁(yè)數(shù)：18 Pages

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德州儀器

具有復(fù)位功能的高速 CMOS 邏輯雙路負(fù)邊沿觸發(fā)式 J-K 觸發(fā)器

? 時(shí)鐘輸入遲滯，改進(jìn)了抗擾度并增加了輸入上升和下降時(shí)間\n? 互補(bǔ)輸出\n? 當(dāng) VCC = 5V， CL = 15pF，TA = 25℃ 時(shí) fMAX 典型值 = 60MHz\n? 標(biāo)準(zhǔn)輸出：10 個(gè) LSTTL 負(fù)載\n? 寬工作溫度范圍：–55℃ 至 125℃\n? 與 LSTTL 邏輯 IC 相比，功耗顯著降低\n? 工作電壓為 2 V 至 6V\n? HCT 類型 \n? 直接 LSTTL 輸入邏輯兼容性， VIL = 0.8V（最大值），VIH = 2V（最小值）\n? CMOS 輸入兼容性，當(dāng)電壓為 VOL、VOH時(shí)，II ≤ 1μA;

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德州儀器

絲?。?a target="_blank" title="Marking" href="/cd54hc73f/marking.html">CD54HC73F；Package：CDIP；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 頁(yè)數(shù)：24 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd54hc73f/marking.html">CD54HC73F；Package：CDIP；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 頁(yè)數(shù)：24 Pages

TI

德州儀器

絲印：5962-8515301CA；Package：CDIP；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 頁(yè)數(shù)：24 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/5962-8515301ca/marking.html">5962-8515301CA；Package：CDIP；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features ? Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times ? Asynchronous reset ? Complementary outputs ? Buffered inputs ? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ ? Fanout (over temperature range) – Standard outputs: 10 LS

文件：1.14847 Mbytes 頁(yè)數(shù)：24 Pages

TI

德州儀器