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          首頁
                >CD54HC112>規(guī)格書列表
                
          
            
          
                
          
                    
          型號(hào)下載 訂購功能描述制造商 上傳企業(yè)LOGO
          
                    
          CD54HC112
          CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger
          
1 Features
? Hysteresis on clock inputs for improved noise
immunity and increased input rise and fall times
? Asynchronous set and reset
? Complementary outputs
? Buffered inputs
? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA
= 25℃
? Fanout (over temperature range)
– Standard output
          文件：1.3793 Mbytes 頁數(shù)：29 Pages
          TI
          德州儀器
          

          CD54HC112
          Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
          文件：757.59 Kbytes 頁數(shù)：20 Pages
          TI
          德州儀器
          

          CD54HC112
          Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
          文件：346.89 Kbytes 頁數(shù)：13 Pages
          TI
          德州儀器
          

          CD54HC112
          Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
          文件：643.79 Kbytes 頁數(shù)：18 Pages
          TI
          德州儀器
          

          CD54HC112
          具有設(shè)置與復(fù)位端的高速 CMOS 邏輯雙路負(fù)邊沿觸發(fā)式 J-K 觸發(fā)器
          The ?HC112 and ?HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.\n\n These flip-flops have independent J, K, Set, Reset, a  ? Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times\n? Complementary Outputs\n? Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C\n? Standard Outputs . . . . . 10 LSTTL Loads\n? Wide Operating Temperature Range . . . –55°C to 125°C\n? Significant Pow;
          TI
          德州儀器
          

          CD54HC112_V01
          CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger
          
1 Features
? Hysteresis on clock inputs for improved noise
immunity and increased input rise and fall times
? Asynchronous set and reset
? Complementary outputs
? Buffered inputs
? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA
= 25℃
? Fanout (over temperature range)
– Standard output
          文件：1.3793 Mbytes 頁數(shù)：29 Pages
          TI
          德州儀器
          

          CD54HC112F3A
          絲?。?a target="_blank" title="Marking" href="/8408801ea/marking.html">8408801EA；Package：CDIP；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger
          
1 Features
? Hysteresis on clock inputs for improved noise
immunity and increased input rise and fall times
? Asynchronous set and reset
? Complementary outputs
? Buffered inputs
? Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA
= 25℃
? Fanout (over temperature range)
– Standard output
          文件：1.3793 Mbytes 頁數(shù)：29 Pages
          TI
          德州儀器
          

          CD54HC112_08
          Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
          文件：643.79 Kbytes 頁數(shù)：18 Pages
          TI
          德州儀器
          

          CD54HC112_15
          Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
          文件：757.59 Kbytes 頁數(shù)：20 Pages
          TI
          德州儀器
          

          CD54HC112F3A
          Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
          文件：643.79 Kbytes 頁數(shù)：18 Pages
          TI
          德州儀器
          

          
            
          
		
        
          
            
          
                
          技術(shù)參數(shù)
          
            
          
            
            
            	
          • Technology Family：
            HC
          • Supply voltage (Min) (V)：
            2
          • Supply voltage (Max) (V)：
            6
          • Input type：
            LVTTL/CMOS
          • Output type：
            Push-Pull
          • Clock Frequency (MHz)：
            20
          • ICC (Max) (uA)：
            80
          • IOL (Max) (mA)：
            -6
          • IOH (Max) (mA)：
            6
          • Features：
            Balanced outputs
          
            
          
        
          
            
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          HARRIS
          		

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          更多CD54HC112供應(yīng)商
            更新時(shí)間2026-1-20 15:01:00
        
          
        
          
          
          
            
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