CDx4HC10 Triple 3-Input NAND Gates

1 Features ? Buffered inputs ? Wide operating voltage range: 2 V to 6 V ? Wide operating temperature range: -55°C to +125°C ? Supports fanout up to 10 LSTTL loads ? Significant power reduction compared to LSTTL logic ICs 2 Applications ? Alarm / tamper detect circuit ? S-R latch 3 D

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德州儀器

High-Speed CMOS Logic Triple 3-Input NAND Gate

文件：265.51 Kbytes 頁數(shù)：10 Pages

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德州儀器

High-Speed CMOS Logic Triple 3-Input NAND Gate

文件：261.209 Kbytes 頁數(shù)：11 Pages

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德州儀器

High-Speed CMOS Logic Triple 3-Input NAND Gate

文件：32.159 Kbytes 頁數(shù)：5 Pages

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德州儀器

High-Speed CMOS Logic Triple 3-Input NAND Gate

文件：614.15 Kbytes 頁數(shù)：15 Pages

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德州儀器

軍用 3 通道、3 輸入、2V 至 6V 與非門

This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y?=? A?●?B?●?C in positive logic. ? Buffered inputs\n? Wide operating voltage range: 2?V?to?6?V\n? Wide operating temperature range: -55°C?to?+125°C\n? Supports fanout up to 10 LSTTL loads\n? Significant power reduction compared to LSTTL logic ICs;

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德州儀器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ? Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times ? Asynchronous Reset ? Complementary Outputs ? Buffered Inputs ? Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC ? Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 頁數(shù)：20 Pages

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德州儀器

絲?。?a target="_blank" title="Marking" href="/5962-8515401ca/marking.html">5962-8515401CA；Package：CDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ? Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times ? Asynchronous Reset ? Complementary Outputs ? Buffered Inputs ? Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC ? Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/5962-8515401ca/marking.html">5962-8515401CA；Package：CDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ? Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times ? Asynchronous Reset ? Complementary Outputs ? Buffered Inputs ? Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC ? Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 頁數(shù)：20 Pages

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德州儀器

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ? Asynchronous Set and Reset ? Schmitt Trigger Clock Inputs ? Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC ? Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads ? Wi

文件：367.45 Kbytes 頁數(shù)：16 Pages

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德州儀器