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          首頁 >CD54ACT373>規(guī)格書列表

          型號(hào)下載 訂購功能描述制造商 上傳企業(yè)LOGO

          CD54ACT373

          Octal Transparent Latch Three-State, Non-Inverting

          Description The CD54AC373/3A and CD54ACT373/3A are octal transparent three-state latches that utilize the Harris Advanced CMOS Logic technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enabl

          文件:9.7 Kbytes 頁數(shù):1 Pages

          INTERSIL

          CD54ACT373

          CDx4AC373, CDx4ACT373 Octal Transparent Latch, 3-State

          1 Features ? SCR-Latchup-resistant CMOS process and circuit design ? Speed of bipolar FAST*/AS/S with significantly reduced power consumption ? Balanced propagation delays ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply ? ±24mA output drive cu

          文件:749.42 Kbytes 頁數(shù):15 Pages

          TI

          德州儀器

          CD54ACT373

          OCTAL TRANSPARENT LATCH, 3-STATE

          文件:233.95 Kbytes 頁數(shù):8 Pages

          TI

          德州儀器

          CD54ACT373

          具有三態(tài)輸出的八路透明鎖存器

          The RCA-CD54/74AC373 and CD54/74AC533 and the CD54/74ACT373 and CD54/74ACT533 octal transparent 3-state latches use the RCA ADVANCED CMOS technology. The outputs are transparent to the inputs when the Latch Enable (LE\\) is HIGH. When the Latch Enable (LE\\) goes LOW, the data is latched. The Output ? Buffered inputs\n? Typical pro-agation delay: 4.3 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF\n? Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015\n? SCR-Latchup-resistant CMOS process and circuit design\n? Speed of bipolar FAST*/AS/S with significantly reduced power consumption\n? Balanced propaga;

          TI

          德州儀器

          CD54ACT3733A

          Octal Transparent Latch Three-State, Non-Inverting

          Description The CD54AC373/3A and CD54ACT373/3A are octal transparent three-state latches that utilize the Harris Advanced CMOS Logic technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enabl

          文件:9.7 Kbytes 頁數(shù):1 Pages

          INTERSIL

          CD54ACT373F3A

          CDx4AC373, CDx4ACT373 Octal Transparent Latch, 3-State

          1 Features ? SCR-Latchup-resistant CMOS process and circuit design ? Speed of bipolar FAST*/AS/S with significantly reduced power consumption ? Balanced propagation delays ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply ? ±24mA output drive cu

          文件:749.42 Kbytes 頁數(shù):15 Pages

          TI

          德州儀器

          CD54ACT373F3A.A

          CDx4AC373, CDx4ACT373 Octal Transparent Latch, 3-State

          1 Features ? SCR-Latchup-resistant CMOS process and circuit design ? Speed of bipolar FAST*/AS/S with significantly reduced power consumption ? Balanced propagation delays ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply ? ±24mA output drive cu

          文件:749.42 Kbytes 頁數(shù):15 Pages

          TI

          德州儀器

          CD54ACT373F3A

          Octal Transparent Latch

          文件:1.26556 Mbytes 頁數(shù):17 Pages

          TI

          德州儀器

          技術(shù)參數(shù)

          • Input type:

            TTL-Compatible CMOS

          • Output type:

            3-State

          • VCC(Min)(V):

            4.5

          • VCC(Max)(V):

            5.5

          • Channels(#):

            8

          • Clock Frequency(Max)(MHz):

            90

          • ICC(uA):

            160

          • IOL(Max)(mA):

            24

          • IOH(Max)(mA):

            -24

          • Rating:

            Military

          • Package Group:

            CDIP

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          更多CD54ACT373供應(yīng)商 更新時(shí)間2026-1-18 8:01:00
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