Dual “J-K” Flip-Flop with Set and Reset

Description The CD54AC112/3A and CD54ACT112/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. The CD54AC112/3A and CD54ACT112/3A are supplied in 16 lead dual-in-line ceramic packages (F suffix).

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INTERSIL

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays 24-mA Output Drive Current Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Me

文件：323.94 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：546.06 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

Dual j-k Flip-Flop with Set and Reset

文件：228.31 Kbytes 頁數(shù)：8 Pages

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德州儀器

具有設(shè)置和復(fù)位端的雙路負(fù)邊沿觸發(fā)式 J-K 觸發(fā)器

The ?ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\\ or clear (CLR)\\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\\ and CLR\\ are inactive (high), data at the J and K inputs meeting the set ? Inputs Are TTL-Voltage Compatible\n? Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption\n? Balanced Propagation Delays\n? ±24-mA Output Drive Current \n? Fanout to 15 F Devices\n \n? SCR-Latchup-Resistant CMOS Process and Circuit Design\n? Exceeds 2-kV ESD Protection Per M;

TI

德州儀器

Dual “J-K” Flip-Flop with Set and Reset

Renesas

瑞薩

絲?。?a target="_blank" title="Marking" href="/cd54act112f3a/marking.html">CD54ACT112F3A；Package：CDIP；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays 24-mA Output Drive Current Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Me

文件：323.94 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

絲印：CD54ACT112F3A；Package：CDIP；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays 24-mA Output Drive Current Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Me

文件：323.94 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：546.06 Kbytes 頁數(shù)：13 Pages

TI

德州儀器

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：546.06 Kbytes 頁數(shù)：13 Pages

TI

德州儀器