| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
絲?。?a target="_blank" title="Marking" href="/cd54ac32f3a/marking.html">CD54AC32F3A；Package：CDIP；CDx4AC32 Quadruple 2-Input Positive-or Gates 1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply ? Buffered inputs ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Balanced propagation delays ? ±24mA output drive current – Fanout to 15 F devices ? S 文件：1.22042 Mbytes 頁數(shù)：24 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd54ac32f3a/marking.html">CD54AC32F3A；Package：CDIP；CDx4AC32 Quadruple 2-Input Positive-or Gates 1 Features ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply ? Buffered inputs ? Speed of bipolar F, AS, and S, with significantly reduced power consumption ? Balanced propagation delays ? ±24mA output drive current – Fanout to 15 F devices ? S 文件：1.22042 Mbytes 頁數(shù)：24 Pages | TI 德州儀器 | TI | ||
Octal Transparent Latch Three-State, Non-Inverting Description The CD54AC373/3A and CD54ACT373/3A are octal transparent three-state latches that utilize the Harris Advanced CMOS Logic technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enabl 文件：9.7 Kbytes 頁數(shù)：1 Pages | INTERSIL | INTERSIL | ||
CDx4AC373, CDx4ACT373 Octal Transparent Latch, 3-State 1 Features ? SCR-Latchup-resistant CMOS process and circuit design ? Speed of bipolar FAST*/AS/S with significantly reduced power consumption ? Balanced propagation delays ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply ? ±24mA output drive cu 文件：749.42 Kbytes 頁數(shù)：15 Pages | TI 德州儀器 | TI | ||
Octal Transparent Latch Three-State, Non-Inverting Description The CD54AC373/3A and CD54ACT373/3A are octal transparent three-state latches that utilize the Harris Advanced CMOS Logic technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enabl 文件：9.7 Kbytes 頁數(shù)：1 Pages | INTERSIL | INTERSIL | ||
CDx4AC373, CDx4ACT373 Octal Transparent Latch, 3-State 1 Features ? SCR-Latchup-resistant CMOS process and circuit design ? Speed of bipolar FAST*/AS/S with significantly reduced power consumption ? Balanced propagation delays ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply ? ±24mA output drive cu 文件：749.42 Kbytes 頁數(shù)：15 Pages | TI 德州儀器 | TI | ||
CDx4AC373, CDx4ACT373 Octal Transparent Latch, 3-State 1 Features ? SCR-Latchup-resistant CMOS process and circuit design ? Speed of bipolar FAST*/AS/S with significantly reduced power consumption ? Balanced propagation delays ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply ? ±24mA output drive cu 文件：749.42 Kbytes 頁數(shù)：15 Pages | TI 德州儀器 | TI | ||
CDx4AC374, CDx4ACT374, CD74AC534 Octal D-Type Flip-Flops, 3-State Positive- Edge Triggered 1 Features ? SCR-Latch-up-resistant CMOS process and circuit design ? Speed of bipolar FAST*/AS/S with significantly reduced power consumption ? Balanced propagation delays ? AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply ? ± 24mA output drive 文件：781.57 Kbytes 頁數(shù)：16 Pages | TI 德州儀器 | TI | ||
Octal D-Type Flip-Flop, Three-State Positive-Edge Triggered, Non-Inverting Description The CD54AC374/3A and CD54ACT374/3A are octal D-type, three-state, positive-edge triggered flip-flops that utilize the Harris Advanced CMOS Logic technology. The eight flipflops enter data into their registers on the LOW-to-HIGH transition of the clock (CP). The Output Enable (OE) cont 文件：9.7 Kbytes 頁數(shù)：1 Pages | INTERSIL | INTERSIL | ||
Octal D-Type Flip-Flop, Three-State Positive-Edge Triggered, Non-Inverting Description The CD54AC374/3A and CD54ACT374/3A are octal D-type, three-state, positive-edge triggered flip-flops that utilize the Harris Advanced CMOS Logic technology. The eight flipflops enter data into their registers on the LOW-to-HIGH transition of the clock (CP). The Output Enable (OE) cont 文件：9.7 Kbytes 頁數(shù)：1 Pages | INTERSIL | INTERSIL |
晶體管資料
- 型號：
- 別名：
三極管、晶體管、晶體三極管
- 生產(chǎn)廠家：
- 制作材料：
- 性質(zhì)：
射頻/高頻放大 （HF）_功率放大 （PA）
- 封裝形式：
直插封裝
- 極限工作電壓：
200V
- 最大電流允許值：
2A
- 最大工作頻率：
<1MHZ或未知
- 引腳數(shù)：
3
- 可代換的型號：
- 最大耗散功率：
25W
- 放大倍數(shù)：
- 圖片代號：
B-91
- vtest：
200
- htest：
999900
- atest：
2
- wtest：
25
技術(shù)參數(shù)
- 精度：
±10%
- 額定電流：
1.42A
- 直流電阻(DCR)：
76mΩ
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
品牌 |
23+ |
7300 |
專注配單,只做原裝進(jìn)口現(xiàn)貨 |
詢價(jià) | |||
TI |
07+ |
CDIP16 |
5000 |
原裝現(xiàn)貨價(jià)格有優(yōu)勢量多可發(fā)貨 |
詢價(jià) | ||
TI |
16+ |
DIP |
132 |
全新原裝現(xiàn)貨 |
詢價(jià) | ||
HAR |
25+ |
2 |
百分百原裝正品 真實(shí)公司現(xiàn)貨庫存 本公司只做原裝 可 |
詢價(jià) | |||
TI |
2015+ |
SOP/DIP |
19889 |
一級代理原裝現(xiàn)貨,特價(jià)熱賣! |
詢價(jià) | ||
TI |
23+ |
CDIP14 |
3700 |
絕對全新原裝!現(xiàn)貨!特價(jià)!請放心訂購! |
詢價(jià) | ||
HARRIS |
2016+ |
CDIP-16 |
8880 |
只做原裝,假一罰十,公司可開17%增值稅發(fā)票! |
詢價(jià) | ||
HAR |
24+ |
18 |
詢價(jià) | ||||
PASSIVE |
1500 |
SUM |
6000 |
詢價(jià) | |||
N/A |
17+ |
NEW |
6200 |
100%原裝正品現(xiàn)貨 |
詢價(jià) |
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