CMOS Dual 64-Stage Static Shift Register

Description CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32rd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted

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INTERSIL

CMOS DUAL 64-STAGE STATIC SHIFT REGISTER

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TI

德州儀器

CMOS Dual 64-Stage Static Shift Register

Description\nCD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32rd, 48th, and 64th stages. These\ntaps also serve as input points allowing data to be inputted at th ? High-Voltage Types (20-Volt Rating)\n? Low Quiescent Current - 10nA/pkg (Typ.) at VDD = 5V\n? Clock Frequency 12MHz (Typ.) at VDD = 10V\n? Schmitt Trigger Clock Inputs Allow Operation with Very Slow Clock Rise and Fall Times\n? Capable of Driving Two Low-power TTL Loads, One Low-power Schottky TTL;

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CMOS 雙 64 位靜態(tài)移位寄存器

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CMOS DUAL 64-STAGE STATIC SHIFT REGISTER

TI

德州儀器

CMOS Dual 64-Stage Static Shift Register

Features: ? Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ? Clock frequency 12 MHz (typ.} at Vpp=10V ? Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

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TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4517be/marking.html">CD4517BE；Package：PDIP；CMOS Dual 64-Stage Static Shift Register

Features: ? Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ? Clock frequency 12 MHz (typ.} at Vpp=10V ? Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

文件：475.92 Kbytes 頁(yè)數(shù)：11 Pages

TI

德州儀器

絲印：CD4517BE；Package：PDIP；CMOS Dual 64-Stage Static Shift Register

Features: ? Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ? Clock frequency 12 MHz (typ.} at Vpp=10V ? Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

文件：475.92 Kbytes 頁(yè)數(shù)：11 Pages

TI

德州儀器

絲印：CD4517BF3A；Package：CDIP；CMOS Dual 64-Stage Static Shift Register

Features: ? Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ? Clock frequency 12 MHz (typ.} at Vpp=10V ? Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

文件：475.92 Kbytes 頁(yè)數(shù)：11 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4517bf3a/marking.html">CD4517BF3A；Package：CDIP；CMOS Dual 64-Stage Static Shift Register

Features: ? Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ? Clock frequency 12 MHz (typ.} at Vpp=10V ? Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

文件：475.92 Kbytes 頁(yè)數(shù)：11 Pages

TI

德州儀器