| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
絲?。?strong>CD4508B；Package：SOP；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages | TI 德州儀器 | TI | ||
絲?。?strong>CD4508B；Package：SOP；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4508bd/3/marking.html">CD4508BD/3；Package：CDIPSB；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages | TI 德州儀器 | TI | ||
絲印：CD4508BD/3；Package：CDIPSB；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4508bf3a/marking.html">CD4508BF3A；Package：CDIP；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4508bf3a/marking.html">CD4508BF3A；Package：CDIP；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4508bm/marking.html">CD4508BM；Package：SOIC；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4508bm/marking.html">CD4508BM；Package：SOIC；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4508bm/marking.html">CD4508BM；Package：SOIC；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages | TI 德州儀器 | TI | ||
絲?。?strong>CD4508B；Package：SOP；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages | TI 德州儀器 | TI |
詳細參數(shù)
- 型號：
CD4508B
- 功能描述：
閉鎖 CMOS DUAL 4-BIT LATCH
- RoHS：
否
- 制造商：
Micrel
- 電路數(shù)量：
1
- 邏輯類型：
CMOS
- 邏輯系列：
TTL
- 極性：
Non-Inverting
- 輸出線路數(shù)量：
9
- 電源電壓-最大：
12 V
- 電源電壓-最小：
5 V
- 最大工作溫度：
+ 85 C
- 最小工作溫度：
- 40 C
- 封裝/箱體：
SOIC-16
- 封裝：
Reel
| 供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
TI |
23+ |
24-SOIC |
15000 |
TI現(xiàn)貨商!原裝正品! |
詢價 | ||
TI |
24+ |
SOP24 |
450 |
詢價 | |||
TI |
23+ |
SOP-24 |
3200 |
絕對全新原裝!優(yōu)勢供貨渠道!特價!請放心訂購! |
詢價 | ||
TI |
24+ |
SOP24 |
5650 |
公司原廠原裝現(xiàn)貨假一罰十!特價出售!強勢庫存! |
詢價 | ||
TI |
25+ |
SOP24 |
368 |
原裝現(xiàn)貨熱賣中,提供一站式真芯服務 |
詢價 | ||
TI |
16+ |
原廠封裝 |
10000 |
全新原裝正品,代理優(yōu)勢渠道供應,歡迎來電咨詢 |
詢價 | ||
TI |
25+23+ |
SOP24 |
32938 |
絕對原裝正品全新進口深圳現(xiàn)貨 |
詢價 | ||
Texas Instruments |
24+ |
24-SO |
56200 |
一級代理/放心采購 |
詢價 | ||
TI/德州儀器 |
2447 |
SOP24 |
100500 |
一級代理專營品牌!原裝正品,優(yōu)勢現(xiàn)貨,長期排單到貨 |
詢價 | ||
TI |
25+ |
SOP-24 |
4854 |
就找我吧!--邀您體驗愉快問購元件! |
詢價 |
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