CMOS Strobed Hex Inverter/Buffer

Description CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic “1” on the OUTPUT DISABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic “1” on the INHIBIT input swit

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INTERSIL

CMOS Strobed Hex Inverter/Buffer

Description\nCD4502BMS consists of six inverter/buffers with 3 state outputs. A logic “1” on the OUTPUT DISABLE input\nproduces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus\nsimplifying system design. A Logic “1” on the INHIBIT input switches all ? High Voltage Type (20V Rating)\n? 2 TTL Load Output Drive Capability\n? 3 State Outputs\n? Common Output Disable Control\n? Inhibit Control\n? 100% Tested for Quiescent Current at 20V\n? 5V, 10V and 15V Parametric Ratings\n? Maximum Input Current of 1μA at 18V Over Full Package Temperature Ran;

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瑞薩

CMOS Strobed Hex Inverter/Buffer

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TI

德州儀器

CMOS Strobed Hex Inverter/Buffer

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TI

德州儀器

CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

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TI

德州儀器