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首頁 >CD450>規(guī)格書列表

型號(hào)	下載訂購	功能描述	制造商上傳企業(yè)	LOGO
CD4504BPWE4	文件：702.45 Kbytes Page：16 Pages	絲印：CM504B；Package：TSSOP；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation Features: ? Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ? Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&# 文件：702.45 Kbytes 頁數(shù)：16 Pages	TI 德州儀器	TI
CD4504BPWR	文件：702.45 Kbytes Page：16 Pages	絲?。?a target="_blank" title="Marking" href="/cm504b/marking.html">CM504B；Package：TSSOP；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation Features: ? Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ? Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&# 文件：702.45 Kbytes 頁數(shù)：16 Pages	TI 德州儀器	TI
CD4504BPWR.A	文件：702.45 Kbytes Page：16 Pages	絲印：CM504B；Package：TSSOP；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation Features: ? Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ? Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&# 文件：702.45 Kbytes 頁數(shù)：16 Pages	TI 德州儀器	TI
CD4504BT	文件：33.24 Kbytes Page：3 Pages	CMOS Hex Voltage Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation Intersil’s Satellite Applications Flow? (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of r 文件：33.24 Kbytes 頁數(shù)：3 Pages	INTERSIL	INTERSIL
CD4508B	文件：650.82 Kbytes Page：17 Pages	CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages	TI 德州儀器	TI
CD4508BD3	文件：650.82 Kbytes Page：17 Pages	絲印：CD4508BD/3；Package：CDIPSB；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages	TI 德州儀器	TI
CD4508BD3.A	文件：650.82 Kbytes Page：17 Pages	絲?。?a target="_blank" title="Marking" href="/cd4508bd/3/marking.html">CD4508BD/3；Package：CDIPSB；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages	TI 德州儀器	TI
CD4508BF3A	文件：650.82 Kbytes Page：17 Pages	絲?。?a target="_blank" title="Marking" href="/cd4508bf3a/marking.html">CD4508BF3A；Package：CDIP；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages	TI 德州儀器	TI
CD4508BF3A.A	文件：650.82 Kbytes Page：17 Pages	絲印：CD4508BF3A；Package：CDIP；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages	TI 德州儀器	TI
CD4508BM	文件：650.82 Kbytes Page：17 Pages	絲印：CD4508BM；Package：SOIC；CMOS Dual 4-Bit Latch Features: ? Two independent 4-bit latches ? Individual master reset for each 4-bit latch ? 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ? 100% tested for quiescent current at 20 V ? 5-V 文件：650.82 Kbytes 頁數(shù)：17 Pages	TI 德州儀器	TI

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詳細(xì)參數(shù)

型號(hào)：
CD450
功能描述：
緩沖器和線路驅(qū)動(dòng)器 Hex 3-STATE Buffer
RoHS：
否
制造商：
Micrel
輸入線路數(shù)量：
1
輸出線路數(shù)量：
2
極性：
Non-Inverting
電源電壓-最大：
+/- 5.5 V
電源電壓-最?。?/span>
+/- 2.37 V
最大工作溫度：
+ 85 C
安裝風(fēng)格：
SMD/SMT
封裝/箱體：
MSOP-8
封裝：
Reel

供應(yīng)商	型號(hào)	品牌	批號(hào)	封裝	庫存	備注	價(jià)格
貿(mào)澤芯城（深圳）電子科技有限公司	CD4503BCM	FAIRCHILD/仙童	23+	SOP-16	10000	原廠授權(quán)一級(jí)代理,專業(yè)海外優(yōu)勢訂貨,價(jià)格優(yōu)勢、品種	詢價(jià)
深圳市福田區(qū)綠盛電子商行	CD4503BCMX	FSC	2015+	SOP	19889	一級(jí)代理原裝現(xiàn)貨,特價(jià)熱賣!	詢價(jià)
深圳市一線半導(dǎo)體有限公司	CD4503BCMX	FSC	24+	SOP	16940		詢價(jià)
深圳市旺財(cái)半導(dǎo)體有限公司	CD4503BCMX	FSC	23+	SOP	3880	正品原裝貨價(jià)格低	詢價(jià)
深圳市昌和盛利電子有限公司	CD4503BCMX	FAIRCHILD	NEW	原廠封裝	9526	代理全系列銷售, 全新原裝正品,價(jià)格優(yōu)勢,長期供應(yīng),量大可訂	詢價(jià)
深圳市聯(lián)世界科技有限公司	CD4503BCN	NATIONAL	24+/25+		210	原裝正品現(xiàn)貨庫存價(jià)優(yōu)	詢價(jià)
深圳市豪邁興電子有限公司	CD4503BCN	FSC	24+	DIP16	5650	公司原廠原裝現(xiàn)貨假一罰十!特價(jià)出售!強(qiáng)勢庫存!	詢價(jià)
深圳市卓越微芯電子有限公司	CD4503BCN	NSC	25+	DIP16	4500	百分百原裝正品真實(shí)公司現(xiàn)貨庫存本公司只做原裝可	詢價(jià)
深圳市億智騰科技有限公司	CD4503BCN	FSC	24+	DIP	6430	原裝現(xiàn)貨/歡迎來電咨詢	詢價(jià)
瀚佳科技(深圳)有限公司	CD4503BCN	ON Semiconductor	24+	16-DIP	65200	一級(jí)代理/放心采購	詢價(jià)

更多CD450供應(yīng)商更新時(shí)間2026-1-18 11:09:00

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