CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

Features: Bm Medium-speed operation — tp = 90 ns; tpLH ? 140 ns {typ.) at TOV INHIBIT and ENABLE inputs : Buffered outputs = 100% tested for quiescent current at 20 V Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (o

文件：815.9 Kbytes 頁(yè)數(shù)：17 Pages

TI

德州儀器

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

文件：828.89 Kbytes 頁(yè)數(shù)：13 Pages

TI

德州儀器

CMOS 可擴(kuò)展 4 寬度 2 輸入與或非門(mén)

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\\) is tied to VSS and ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is requir ? Medium-speed operation - tPHL = 90 ns; tPLH = 140 ns (typ.) at 10 V\n? INHIBIT and ENABLE inputs\n? Buffered outputs\n? 100% tested for quiescent current at 20 V\n? Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Noise margin (over full pac;

TI

德州儀器

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

文件：85.83 Kbytes 頁(yè)數(shù)：9 Pages

INTERSIL

CMOS EXPANDABLE 4-WIDE 2-INPUT AND-OR-INVERT GATE

文件：539.57 Kbytes 頁(yè)數(shù)：12 Pages

TI

德州儀器

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

文件：828.89 Kbytes 頁(yè)數(shù)：13 Pages

TI

德州儀器