CMOS AND GATES

文件：530.84 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

CMOS AND Gates

文件：1.42989 Mbytes 頁數(shù)：29 Pages

TI

德州儀器

CMOS AND Gates

文件：1.42989 Mbytes 頁數(shù)：29 Pages

TI

德州儀器

2 通道、4 輸入、3V 至 18V 與門

CD4073B, CD4081B and CD4082B AND gates, provide the system designer with direct implementation of the ANDfunction and supplement the existing family of CMOS gates.\n\n The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages(F3A suffix), 14-lead dual-in- ? Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V\n? Maximum input current of 1 μA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C\n? 1 V at VDD = 5 V\n? 2.5 V at VDD = 15 V\n? Standardized, symmetrical output characteristics\n? Meets all requirements of JEDEC T;

TI

德州儀器

4000系列邏輯芯片

HGSEMI

華冠

軍用 2 通道、4 輸入、3V 至 18V 與門

CD4073B, CD4081B and CD4082B AND gates, provide the system designer with direct implementation of the ANDfunction and supplement the existing family of CMOS gates.\n\n The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages(F3A suffix), 14-lead dual-in- ? Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V\n? Maximum input current of 1 μA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C\n? 1 V at VDD = 5 V\n? 2.5 V at VDD = 15 V\n? Standardized, symmetrical output characteristics\n? Meets all requirements of JEDEC T;

TI

德州儀器

Package：14-DIP（0.300"，7.62mm）；包裝：卷帶（TR） 類別：集成電路（IC） 門和反相器 描述：IC GATE AND 2CH 4-INP 14DIP

TI

德州儀器

Package：14-SOIC（0.154"，3.90mm 寬）；包裝：管件 類別：集成電路（IC） 門和反相器 描述：IC GATE AND 2CH 4-INP 14SOIC

TI

德州儀器

Package：14-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 門和反相器 描述：IC GATE AND 2CH 4-INP 14SOIC

TI

德州儀器