CMOS OR Gate

Description CD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. The CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages: Featu

文件：114.68 Kbytes 頁數(shù)：10 Pages

INTERSIL

CMOS OR GATES

文件：209.38 Kbytes 頁數(shù)：5 Pages

TI

德州儀器

CMOS OR Gate

Description\nCD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.\nThe CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages: ? High-Voltage Types (20V Rating)\n? CD4071BMS Quad 2-Input OR Gate\n? CD4072BMS Dual 4-Input OR Gate\n? CD4075BMS Triple 3-Input OR Gate\n? Medium Speed Operation:\n- tPHL, tPLH = 60ns (typ) at 10V\n? 100% Tested for Quiescent Current at 20V\n? Maximum Input Current of 1μA at 18V Over Full Pack;

Renesas

瑞薩

雙四路或門

正雙四路輸入,工作電壓（Vcc）(v)3~15V,靜態(tài)電流Iq(Typ)0.01uA

XBLW

芯伯樂

Dual 4-input OR gate

I-CORE

中微愛芯

CMOS OR Gate

Description CD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. The CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages: Featu

文件：114.68 Kbytes 頁數(shù)：10 Pages

INTERSIL

CMOS OR Gate

Features ? High-Voltage Types (20V Rating) ? CD4071BMS Quad 2-Input OR Gate ? CD4072BMS Dual 4-Input OR Gate ? CD4075BMS Triple 3-Input OR Gate ? Medium Speed Operation: - tPHL, tPLH = 60ns (typ) at 10V ? 100 Tested for Quiescent Current at 20V ? Maximum Input Current of 1?A at 18V Over Fu

文件：396.79 Kbytes 頁數(shù)：11 Pages

RENESAS

瑞薩

CMOS OR Gates

文件：1.63591 Mbytes 頁數(shù)：29 Pages

TI

德州儀器

CMOS OR GATES

文件：209.38 Kbytes 頁數(shù)：5 Pages

TI

德州儀器

CMOS OR GATES

文件：524.26 Kbytes 頁數(shù)：12 Pages

TI

德州儀器