CMOS 8 Input NAND/AND Gate

Description CD4068BMS NAND/AND gate provides the system designer with direct implementation of the positive logic 8 Input NAND and AND functions and supplements the existing family of CMOS gates. Features ? High Voltage Type (20V Rating) ? Medium Speed Operation - TPHL, TPLH = 75n

文件：65.54 Kbytes 頁數(shù)：8 Pages

INTERSIL

CMOS 8-INPUT NAND AND GATE

文件：182.5 Kbytes 頁數(shù)：10 Pages

TI

德州儀器

CMOS 8 Input NAND/AND Gate

Description\nCD4068BMS NAND/AND gate provides the system designer with direct implementation of the positive logic 8 Input NAND and AND functions and supplements the existing family of CMOS gates. ? High Voltage Type (20V Rating)\n? Medium Speed Operation\n- TPHL, TPLH = 75ns (Typ.) at VDD = 10V\n? Buffered Inputs and Outputs\n? 5V, 10V and 15V Parametric Ratings\n? Standardized Symmetrical Output Characteristics\n? 100% Tested for Quiescent Current at 20V\n? Maximum Input Current of 1μA ;

Renesas

瑞薩

8輸入與門/與非門

The CD4068 is an 8-input And Gate/Nand Gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VD ? Wide supply voltage range from 3V to 15V\n? Fully static operation\n? 5V, 10V, and 15V parametric ratings\n? Standardized symmetrical output characteristics\n? Inputs and outputs are protected against electrostatic effects\n? Specified from -40℃ to +125℃\n? Packaging information: DIP14/SOP14/TSSOP;

I-CORE

中微愛芯

CMOS 8-INPUT NAND AND GATE

TI

德州儀器

CMOS 8-Input NAND/AND Gate

Features: Medium-Speed Operation: tPHL, tPLH = 75 ns (typ.) at Vpp = 10 V = Buffered inputs and outputs 5.V, 10-V, and 15-V parametric ratings Standardized symmetrical output characteristics = 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 V over ful

文件：962.58 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4068be/marking.html">CD4068BE；Package：PDIP；CMOS 8-Input NAND/AND Gate

Features: Medium-Speed Operation: tPHL, tPLH = 75 ns (typ.) at Vpp = 10 V = Buffered inputs and outputs 5.V, 10-V, and 15-V parametric ratings Standardized symmetrical output characteristics = 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 V over ful

文件：962.58 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4068be/marking.html">CD4068BE；Package：PDIP；CMOS 8-Input NAND/AND Gate

Features: Medium-Speed Operation: tPHL, tPLH = 75 ns (typ.) at Vpp = 10 V = Buffered inputs and outputs 5.V, 10-V, and 15-V parametric ratings Standardized symmetrical output characteristics = 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 V over ful

文件：962.58 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4068be/marking.html">CD4068BE；Package：PDIP；CMOS 8-Input NAND/AND Gate

Features: Medium-Speed Operation: tPHL, tPLH = 75 ns (typ.) at Vpp = 10 V = Buffered inputs and outputs 5.V, 10-V, and 15-V parametric ratings Standardized symmetrical output characteristics = 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 V over ful

文件：962.58 Kbytes 頁數(shù)：20 Pages

TI

德州儀器

絲?。?a target="_blank" title="Marking" href="/cd4068bf/marking.html">CD4068BF；Package：CDIP；CMOS 8-Input NAND/AND Gate

Features: Medium-Speed Operation: tPHL, tPLH = 75 ns (typ.) at Vpp = 10 V = Buffered inputs and outputs 5.V, 10-V, and 15-V parametric ratings Standardized symmetrical output characteristics = 100% tested for quiescent current at 20 V. Maximum input current of 1 uA at 18 V over ful

文件：962.58 Kbytes 頁數(shù)：20 Pages

TI

德州儀器