CMOS Micropower Phase-Locked Loop

Features: Very low power consumption: 70 4W (typ.) at VCO f, = 10 kHz, Vpp = 5 V = Operating frequency range up to 1.4 MHz (typ.) atVpp=10V, RI =5kQ Low frequency drift: 0.04%/°C (typ.) at Vpp = 10 V Choice of two phase comparators: Exclusive-OR network (1) Edge-controlled memory ne

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德州儀器

CMOS Micropower Phase-Locked Loop

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德州儀器

CMOS 微功耗鎖相環(huán)

CD4046B CMOS Micropower Phase-Locked Loop (PLL) consists of a low-power, linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal-input amplifier and a common comparator input. A 5.2-V zener diode is provided for supply regulation if necessary.\n The CD40 ? Very low power consumption: ???70 μW (typ.) at VCO fo = 10 kHz, VDD = 5 V\n? Low frequency drift: 0.04%/°C (typ.) at VDD = 10 V\n? Edge-controlled memory network with phase-pulse output for lock indication (II)\n? VCO inhibit control for ON-OFF keying and ultra-low standby power consumption\n?;

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德州儀器

CMOS Micropower Phase Locked Loop

Description CD4046BMS CMOS Micropower Phase-Locked Loop (PLL) consists of a low power linear voltage-controlled oscillator (VCO) and two different phase comparators having a common signal input amplifier and a common comparator input. A 5.2V zener diode is provided for supply regulation if nece

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INTERSIL

CMOS MICROPOWER PHASE-LOCKED LOOP

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德州儀器

CMOS Micropower Phase-Lockedn Loop

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德州儀器