CMOS Quad Clocked D Latch

文件：1.87567 Mbytes 頁數(shù)：30 Pages

TI

德州儀器

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes 頁數(shù)：30 Pages

TI

德州儀器

CMOS Quad Clocked D Latch

文件：599.48 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes 頁數(shù)：30 Pages

TI

德州儀器

CMOS Quad Clocked D Latch

文件：1.87567 Mbytes 頁數(shù)：30 Pages

TI

德州儀器

CMOS Quad Clocked D Latch

文件：599.48 Kbytes 頁數(shù)：12 Pages

TI

德州儀器

CMOS 四路時鐘控制“D”鎖存器

CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.\n\n Information present at the data input is transfe ? Clock polarity control\n? Common Clock\n? Standardized, symmetrical output characteristics\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Noise margin (full package-temperature range) = ????????1 V at VDD = 5 V ????????2 V at VDD = 10 V ??;

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德州儀器

CMOS Quad D Latch, Clocked

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Renesas

瑞薩

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 鎖存器 描述：IC QUAD CLOCKED D LATCH 16SOIC

TI

德州儀器

Package：16-SOIC（0.154"，3.90mm 寬）；包裝：卷帶（TR） 類別：集成電路（IC） 鎖存器 描述：IC QUAD CLOCKED D LATCH 16-SOIC

TI

德州儀器