| 型號 | 下載 訂購 | 功能描述 | 制造商 上傳企業(yè) | LOGO |
|---|---|---|---|---|
絲?。?strong>CD4029B;Package:SOP;CMOS Presettable Up/Down Counter Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d 文件:1.02221 Mbytes 頁數(shù):22 Pages | TI 德州儀器 | TI | ||
絲印:CD4029B;Package:SOP;CMOS Presettable Up/Down Counter Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d 文件:1.02221 Mbytes 頁數(shù):22 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4029be/marking.html">CD4029BE;Package:PDIP;CMOS Presettable Up/Down Counter Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d 文件:1.02221 Mbytes 頁數(shù):22 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4029be/marking.html">CD4029BE;Package:PDIP;CMOS Presettable Up/Down Counter Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d 文件:1.02221 Mbytes 頁數(shù):22 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4029bf/marking.html">CD4029BF;Package:CDIP;CMOS Presettable Up/Down Counter Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d 文件:1.02221 Mbytes 頁數(shù):22 Pages | TI 德州儀器 | TI | ||
絲印:CD4029BF;Package:CDIP;CMOS Presettable Up/Down Counter Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d 文件:1.02221 Mbytes 頁數(shù):22 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4029bm/marking.html">CD4029BM;Package:SOIC;CMOS Presettable Up/Down Counter Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d 文件:1.02221 Mbytes 頁數(shù):22 Pages | TI 德州儀器 | TI | ||
絲?。?a target="_blank" title="Marking" href="/cd4029bm/marking.html">CD4029BM;Package:SOIC;CMOS Presettable Up/Down Counter Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d 文件:1.02221 Mbytes 頁數(shù):22 Pages | TI 德州儀器 | TI | ||
絲印:CD4029BM;Package:SOIC;CMOS Presettable Up/Down Counter Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d 文件:1.02221 Mbytes 頁數(shù):22 Pages | TI 德州儀器 | TI | ||
絲?。?strong>CD4029B;Package:SOP;CMOS Presettable Up/Down Counter Features: ? Medium-speed operation . . . 8 MHz (typ.) @Cy_ = 50 pF and Vpp—Vgg = 10 V # Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times = “Preset Enable” and individual “Jam” inputs provided ? Binary or d 文件:1.02221 Mbytes 頁數(shù):22 Pages | TI 德州儀器 | TI |
| 供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
Texas Instruments |
24+ |
16-SO |
56200 |
一級代理/放心采購 |
詢價 | ||
TI |
25+ |
SOP-16 |
4000 |
就找我吧!--邀您體驗愉快問購元件! |
詢價 | ||
TI |
22+ |
16SO |
9000 |
原廠渠道,現(xiàn)貨配單 |
詢價 | ||
Texas Instruments |
2022+ |
原廠原包裝 |
8600 |
全新原裝 支持表配單 中國著名電子元器件獨立分銷 |
詢價 | ||
TI |
23+ |
16-SO |
3115 |
正品原裝貨價格低 |
詢價 | ||
TI/德州儀器 |
23+ |
16-TSSOP |
20000 |
原廠授權(quán)一級代理,專業(yè)海外優(yōu)勢訂貨,價格優(yōu)勢、品種 |
詢價 | ||
Texas Instruments |
23+ |
16-TSSOP |
7300 |
專注配單,只做原裝進口現(xiàn)貨 |
詢價 | ||
Texas Instruments |
25+ |
16-TSSOP(0.173 4.40mm 寬) |
9350 |
獨立分銷商 公司只做原裝 誠心經(jīng)營 免費試樣正品保證 |
詢價 | ||
TI |
25+ |
16-TSSOP |
20948 |
樣件支持,可原廠排單訂貨! |
詢價 | ||
TI |
25+ |
16-TSSOP |
21000 |
正規(guī)渠道,免費送樣。支持賬期,BOM一站式配齊 |
詢價 |
相關(guān)芯片絲印
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相關(guān)庫存
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